Digital camera interface (DCMI)
RM0090
460/1731
DocID018909 Rev 11
8-bit data
When EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSB’s at its
input (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to
capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4
th
captured data byte is placed in the MSB position in the 32-bit word.
gives an
example of the positioning of captured data bytes in two 32-bit words.
10-bit data
When EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit
data at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The
remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero.
So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
nd
captured data are placed in the MSB position in the 32-bit word as shown in
12-bit data
When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the
12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
nd
captured data are placed in the MSB position in the 32-bit word as shown in
14-bit data
When EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the
14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit
Table 79. Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address
31:24
23:16
15:8
7:0
0
D
n+3
[7:0]
D
n+2
[7:0]
D
n+1
[7:0]
D
n
[7:0]
4
D
n+7
[7:0]
D
n+6
[7:0]
D
n+5
[7:0]
D
n+4
[7:0]
Table 80. Positioning of captured data bytes in 32-bit words (10-bit width)
Byte address
31:26
25:16
15:10
9:0
0
0
D
n+1
[9:0]
0
D
n
[9:0]
4
0
D
n+3
[9:0]
0
D
n+2
[9:0]
Table 81. Positioning of captured data bytes in 32-bit words (12-bit width)
Byte address
31:28
27:16
15:12
11:0
0
0
D
n+1
[11:0]
0
D
n
[11:0]
4
0
D
n+3
[11:0]
0
D
n+2
[11:0]