1 Intro
2
Electrocardiogram (
Ecg
) Signals
The Electrocardiogram (
Ecg
)
•
Ecg
: electrical manifestation of heart activity recorded
from the body surface
•
monitoring of heart rate
The
Ecg
signal can be recorded fairly easily with surface
electrodes placed on the limbs and/or the chest, see pages
6
–
16
below.
Josef Goette
2
2009
4 Peripherals
4.16.3 Pinning
SPI1
Wire
GPIO
Pin
NSS
PA4
20
SCK
PA5
21
MISO
PA6
22
MOSI
PA7
23
SPI2
Wire
GPIO
Pin
NSS
PB12
33
SCK
PB13
34
MISO
PB14
35
MOSI
PB15
36
Figure 4.23:
SPI Connection between a Master a Slave
RM0008
Serial peripheral interface (SPI)
Doc ID 13902 Rev 9
589/995
23.3
SPI functional description
23.3.1 General
description
The block diagram of the SPI is shown in
Figure 207
.
Figure 207. SPI block diagram
Usually, the SPI is connected to external devices through 4 pins:
●
MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
●
MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
●
SCK: Serial Clock output for SPI masters and input for SPI slaves.
●
NSS: Slave select. This is an optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode.
A basic example of interconnections between a single master and a single slave is
illustrated in
Figure 208
.
MOSI
MISO
Baud rate generator
SCK
Master control logic
Communication
control
SPE BR2
BR1
BR0
MSTR CPOL CPHA
BR[2:0]
RXNE
LSB
BIDI
MODE
BIDI
OE
SSM
SSI
BSY
OVR
MOD
RXNE
TXE
ERR
TXE
0
0
DFF
0
SSOE
CRC
EN
0
RX
ONLY
CRC
Next
CRC
ERR
0
1
NSS
IE
F
FIRST
SPI_CR1
SPI_CR2
SPI_SR
TXDM
AEN
RXDM
AEN
IE
IE
Address and data bus
Read
Rx buffer
Shift register
LSB first
Tx buffer
Write
ai14744
Figure 4.24:
SPI Driver
46
STM32 Cortex-M3 Tutorial