DDR memory controller (MPMC)
RM0082
142/844
Doc ID 018672 Rev 1
10.8.4 User-defined
registers
Memory Controller contains two user-defined parameters. These register-width size
parameters hold user-defined values that will be available as output signals
param_user_def_reg_X (X is 0 or 1) at the Memory Controller core (stp_memcd) level.
These parameters have no effect on the Memory Controller except that utilizing addresses
in the register map.
Only a single bit of the user-defined registers is used in this configuration. All other bits of
user_def_reg_0 and user_def_reg_1 are available if customer hookup is required.
Bit 0 of user_def_reg_0 controls the READ data retime function. This function provides the
user with a choice in clock synchronization paths in the PHY.
An alternative path has been created allowing the PHY to synchronize the READ data to the
core clock domain and then pass the data to the read FIFO synchronously, i.e. in 1one clock
cycle. This constrains the 1/4 cycle path for clock synchronization within the PHY between
two flip-flops which are easily co-located, however it adds a cycle of latency to the path.
Bit 0 of user_def_reg_0 allows the user to select the desired path. If the bit is cleared to
1'b0, the alternative path is used and synchronization occurs in the PHY, incurring the extra
cycle of latency. If the bit is set to 1'b1, the standard path is used.
10.9 Address
mapping
The Memory Controller automatically maps user addresses to the DRAM memory in a
contiguous block. Address map begins at user address 0 and finishes at the highest
available address according to the size and number of DRAM devices present. This
mapping is dependent on how the Memory Controller is configured and how the parameters
in the internal Memory Controller registers are programmed (
). The exact
number and values of these parameters depends on the configuration and the type of
memory for which the Memory Controller was designed.
The mapping of the address space to the internal data storage structure of the DRAM
devices is based on the actual size of the DRAM devices available. The size is stored in
user-programmable parameters that must be initialized at power up. Certain DRAM devices
allow for different mapping options to be chosen, while other DRAM devices depend on the
burst length chosen.
10.9.1 DDR
SDRAM
address mapping options
The address structure of DDR SDRAM devices contains five fields. Each of these fields can
be individually addressed when accessing the DRAM. The address map for this Memory
Controller is ordered as follows:
“Chip Select - Row - Bank - Column - Datapath”
The maximum widths of the fields are based on the configuration settings. The actual widths
of the fields may be smaller if the device address width parameters (addr_pins,
eight_bank_mode and column_size) are programmed differently.
