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RM0365
General-purpose timers (TIM2/TIM3/TIM4)
618
Figure 232. Master/Slave timer example
Using one timer as prescaler for another timer
For example, you can configure TIM3 to act as a prescaler for TIM2. Refer to
. To
do this:
1.
Configure TIM3 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM3_CR2 register, a rising edge is
output on TRGO each time an update event is generated.
2. To connect the TRGO output of TIM3 to TIM2, TIM2 must be configured in slave mode
using ITR2 as internal trigger. You select this through the TS bits in the TIM2_SMCR
register (writing TS=010).
3. Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes TIM2 to be clocked by the rising edge of the
periodic TIM3 trigger signal (which correspond to the TIM3 counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note:
If OCx is selected on TIM
3
as the trigger output (MMS=1xx), its rising edge is used to clock
the counter of TIM2.
Using one timer to enable another timer
In this example, we control the enable of TIM2 with the output compare 1 of Timer 3. Refer
to
for connections. TIM2 counts on the divided internal clock only when OC1REF
of TIM3 is high. Both counter clock frequencies are divided by 3 by the prescaler compared
to CK_INT (f
CK_CNT
= f
CK_INT
/3).
1.
Configure TIM3 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM3_CR2 register).
2. Configure the TIM3 OC1REF waveform (TIM3_CCMR1 register).
3. Configure TIM2 to get the input trigger from TIM3 (TS=010 in the TIM2_SMCR
register).
4. Configure TIM2 in gated mode (SMS=101 in TIM2_SMCR register).
5. Enable TIM2 by writing ‘1 in the CEN bit (TIM2_CR1 register).
6. Start TIM3 by writing ‘1 in the CEN bit (TIM3_CR1 register).
Note:
The counter 2 clock is not synchronized with counter 1, this mode only affects the TIM2
counter enable signal.
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