DocID026902 Rev 3
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UM1817
Hardware layout and configuration
57
2.5 Reset
source
The reset signal of STM32091C-EVAL evaluation board is low active and the reset sources
include:
•
Reset button B1
•
Debugging tools from SWD connector CN10 and CN11
•
Daughterboard from CN7
•
Embedded ST-LINK/V2-1
•
RS-232 connector CN9 for ISP.
Note:
The jumper JP11 must be closed for RESET handled by pin 8 of the RS-232 connector CN9
(CTS signal). Refer to
for details.
2.6 Boot
option
The STM32091C-EVAL evaluation board is able to boot from:
•
Embedded user Flash
•
System memory with boot loader for ISP
•
Embedded SRAM for debugging
The boot option is configured by setting one jumper cap on CN7 between pin 22 and pin 24
and one option bit (see
).
The BOOT0 can also be configured via RS-232 connector CN9, as shown in
SB14
PF1 is connected to 8MHz crystal when SB14 is open.
(Default setting)
PF1 is connected to extension connector CN7 when SB14 is closed. In such case
R56 must be removed to avoid disturbance due to the 8 Mhz quartz.
Table 6. 8MHz crystal X2 related solder bridges (continued)
Table 7. Boot related switch
Switch
configuration
bit12 in USER
OPTION BYTES
Boot from
CN7 pin 22 and
pin 24 opened
X
STM32091C-EVAL boot from User Flash. (Default setting)
CN7 pin 22 and
pin 24 closed by
jumper
0
STM32091C-EVAL boot from Embedded SRAM.
CN7 pin 22 and
pin 24 closed by
jumper
1
STM32091C-EVAL boot from System Memory.
