Standart Horizont HX500S, Руководство по обслуживанию, Страница: 8 / 28

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comparative frequency divider and reference frequency
divider to set a frequency dividing ratio for each. An 11.7
MHz reference signal produced by X1001 is input to REF
pin 1 of the PLL IC. The internal reference frequency di-
vider divides the 11.7 MHz reference by 2,340 (or 1,872)
to obtain a reference frequency of 5 kHz (or 6.25 kHz),
which is applied to the phase comparator. Meanwhile, a
sample of the output of VCO
Q1040 is input to the PLL
IC, where it is frequency-divided by the internal compar-
ative frequency divider to produce a comparative frequen-
cy also applied to the phase comparator. The phase com-
parator compares the phase between the reference fre-
quency and comparative frequency to output a pulse cor-
responding to the phase difference between them. This
Circuit Description
pulse is input to the charge pump, and the output from
the charge pump passes through a loop filter composed
of L1005, R1142, C1098, R1143, C1104, R1151, and C1110,
which convert the pulse into a corresponding smoothed
varactor control voltage (VCV). The VCV is applied to
varactor
D1015 ( 1SV325 ) in the VCO tank circuit to elim-
inate phase difference between the reference frequency
and comparative frequency, and so locking the VCO os-
cillation frequency to the reference crystal. The VCO fre-
quency is determined by the frequency-dividing ratio sent
from the CPU to the PLL IC. During receiver power save
operation, the PLL circuit operates intermittently to re-
duce current consumption, for which the intermittent op-
eration control circuit reduces the lock-up time.