Standard Horizon HX270S, Руководство по обслуживанию

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If a CDCSS code is enabled for transmission, the code is
generated by
Q1043 ( HD64F38024W ) and delivered to
X1001 (21.25 MHz) for CDCSS modulating.
The modulated signal from the VCO Q1012 ( 2SC5231 ) is
buffered by Q1013 ( 2SC5374 ). The low-level transmit sig-
nal is then passes through the TX switching diode D1010
( DAN235E ) to the buffer amplifier Q1031 ( 2SC5226 ), driv-
er amplifier Q1034 ( 2SK3074 ), then amplified transmit
signal is applied to the final amplifier
Q1036
( RD07MVS1 )
up to 5.0 watts output power.
The transmit signal passes through the low-pass filtere
and antenna switch
D1031
( RLS135 ), and then the trans-
mit signal is low-pass filtered to suppress harmonic spu-
rious radiation before delivery to the antenna.
4-1 Automatic Transmit Power Control
Current from the final amplifier is sampled by C1238,
C1239, C1242 and C1244, and R1261, and R1267, and is
rectified by
D1032
( 1SS321 ). The resulting DC is fed back
through Q1003 ( LM2904PW ) to the drive amplifier Q1034
( 2SK3074 ) and final amplifier Q1036 ( RD07MVS1 ), for
control of the power output.
The microprocessor selects ”High” or “Low” power lev-
els.
4-2 Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to final transmitting frequency, modulated directly in the
transmit VCO. Additional harmonic suppression is pro-
vided by a low-pass filter consisting of coils L1012 and
L1013 plus capacitors C1148, C1153, C1154, C1159, C1163
and C1172, resulting in more than 60 dB of harmonic sup-
pression prior to delivery to the antenna.
5. PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO Q1012
( 2SC5231 ), VCO buffer Q1013 ( 2SC5374 ), PLL subsystem
IC Q1015 (
MB15A01PFV1
), which contains a reference
divider, serial-to-parallel data latch, programmable divid-
er, phase comparator and charge pump, and crystal X1001
which frequency stability is ±5 ppm –30 °C to +60 °C.
While receiving, VCO Q1012 ( 2SC5231 ) oscillates be-
tween 134.35 and 141.575 MHz according to the transceiv-
er version and the programmed receiving frequency. The
VCO output is buffered by
Q1020 ( 2SC5374 ), then ap-
plied to the prescaler section of Q1015 ( MB15A01PFV1 ).
There the VCO signal is divided by 64 or 65, according to
a control signal from the data latch section of
Q1015
( MB15A01PFV1 ), before being sent to the programmable
divider section of Q1015 ( MB15A01PFV1 ).
The data latch section of Q1015 ( MB15A01PFV1 ) also re-
ceives serial dividing data from the microprocessor Q1043
( HD64F38024W ), which causes the pre-divided VCO sig-
nal to be further divided in the programmable divider
section, depending upon the desired receive frequency,
so as to produce a 5.0 kHz or 6.25 kHz derivative of the
current VCO frequency.
Meanwhile, the reference divider sections of Q1015
( MB15A01PFV1 ) divides the 21.25 MHz crystal reference
from the reference oscillator section of Q1015
( MB15A01PFV1 ), by 3360 (or 2688) to produce the 5.0 kHz
(or 6.25 kHz) loops reference (respectively).
The 5.0 kHz (or 6.25 kHz) signal from the programmable
divider (derived from the VCO) and that derived from
the reference oscillator are applied to the phase detector
section of microprocessor
Q1043 ( HD64F38024W ), which
produces a pulsed output with pulse duration depend-
ing on the phase difference between the input signals.
This pulse train is filtered to DC and returned to the Var-
actor diode
D1004 ( HVC350B ).
Changes in the level of the DC voltage applied to the Var-
actor, affecting the reference in the tank circuit of the VCO
according to the phase difference between the signals de-
rived from the VCO and the crystal reference oscillator.
The VCO is thus phase-locked to the crystal reference os-
cillator. The output of the VCO
Q1012 ( 2SC5231 ) after
buffering by
Q1013
( 2SC5374 ) is applied to the first mix-
er as described previously.
For transmission, the VCO Q1012 ( 2SC5231 ) oscillates
between 156.025 and 157.425 MHz according to the mod-
el version and programmed transmit frequency. The re-
mainder of the PLL circuitry is shared with the receiver.
However, the dividing data from the microprocessor is
such that the VCO frequency is at the actual transmit fre-
quency (rather than offset for IFs, as in the receiving case).
Also, the VCO is modulated by the speech audio applied
to
D1006 ( HSC277 ), as described previously.
6. Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the internal microphone is connected
to
Q1007 ( DTA144EE ), so that when the PTT switch is
closed, pin 19 of microprocessor Q1043 ( HD64F38024W )
goes high. This signal disables the receiver by disabling
the 5 V supply bus at
Q1027 (
DTA144EE
) to the front-
end, FM IF subsystem IC Q1033 ( NJM2591V ).
At the same time, Q1024 ( 2SA1774 ) and Q1025 ( UMW1 )
activate the transmit 5 V supply line to enable the trans-
mitter.
Circuit Description