Figure 6.
USB Type-C™ receptacle (CN1) and ESDA25P35-1U1M TVS diode (D1)
C13
2.2uF 50V
GND
D1
ESDA25P35-1U1M
TP2
SH22
VBUS
GND
GND
TP5
TP3
C1
330pF 50V
CN1
ConUSB31_632723300011_recept
CC1
A5
Dn1
A7
Dp1
A6
G
N
D
1
G
N
D
1
G
N
D
2
G
N
D
2
GND3
A1
GND5
A12
GND6
B12
SBU1
A8
S
H
E
LL
1
S
H
E
L
L
1
S
H
E
LL
2
S
H
EL
L
2
S
H
E
LL
3
SH
E
L
L
3
S
H
E
LL
4
SH
E
L
L
4
S
H
E
LL
5
SH
E
L
L
5
S
H
E
LL
6
SH
E
L
L
6
SSRXn1
B10
SSRXn2
A10
SSRXp1
B11
SSRXp2
A11
SSTXn1
A3
SSTXp1
A2
VBUS1
A4
VBUS2
A9
VBUS4
B9
Dn2
B7
Dp2
B6
GND4
B1
SBU2
B8
SSTXn2
B3
SSTXp2
B2
VBUS3
B4
CC2
B5
TP4
C2
330pF 50V
TP1
CC1c
CC2c
TVS diode (D1) protects the V
BUS
power line and, consequently, the entire system against
electrical overstress (EOS) when you connect a sink through the USB Type-C™ cable.
To be compliant with the USB Power Delivery standard requirements, the board embeds the 330 pF C1 and C2
capacitors, as well as the 2.2 µF C13 capacitor, which ensures a good system robustness.
1.2.2
USB 2.0 data path and configuration settings
The
development boards that feature a USB 2.0
peripheral to expose the D+/D- lines on the USB Type-C™ receptacle (CN1).
Most STM32 Nucleo-64 development boards feature this functionality on the CN10-12 and CN10-14 pins of
the ST morpho connectors. The
,
development boards, instead, map USB 2.0 data on CN10-33 and CN10-17 pins.
Two couples of resistances are connected to the
(U3) USB 2.0 data line protection to extend the
use of this peripheral to all the STM32 Nucleo-64 development boards.
Figure 7.
USB2.0 data line protection ECMF02-2AMX6 (U3) and resistor setup
GND
DP_G4
DP_XX
DM_G4
CC1_G4
ESD
ESD
ESD
ESD
D-
GND
D-
D+
D+
NC
R19
0
SH13
SH11
R20
0
SH22
D+ecmf
D-ecmf
90 ohms
ZDiff
90 ohms
ZDiff
ECMF02-2AMX6
U3
DM_xx
DP_xx
UM2973
Hardware architecture
UM2973
-
Rev 1
page 6/25