ST TDA911 Series, Примечание к применению

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AN1290 Vertical Section
5.1.4 Sync Detection
This part is best explained after the oscillator section since the sawtooth is used for polarity
recognition as shown in
Figure 7 .
Incoming sync pulses are detected by a comparator with 1.6V threshold, which makes it TTL
compatible. Alternately, they may come from the Composite sync signal via the sync extractor.
Each transition on the Vsync input (positive or negative) triggers a very short (6 µs) pulse. The first
short pulse triggers the sampling, then the discharge of C
o
, as explained above. Later, any short
pulse will be ignored until the sawtooth exceeds the 2.5V threshold (defining a “dead zone” of
0.5 / 3 = 16.7% of the period).
In case the first detected edge proved incorrect (i.e. a sync pulse back edge instead of the front
edge), the next discharge is triggered by the front edge, regardless of the polarity of the sync pulse.
This mechanism fails if the sync pulse duration is too long; hence the limit of 15% for V sync duty
factor.
End of Vsync
When the Vsync pulse disappears, the oscillator capacitor charges up to 7V (with a decreasing
slope of above 5.4V). When the capacitor reaches the 7V level, there are no longer any sync pulses,
switches S and NoS revert to their initial position and the frequency reverts to free-running mode.
Figure 7: Sync Detection
Positive or
Negative sync
6µs 6µs Edge detector
Sampling pulse 13µs
Internal sync pulse
Oscillator capacitor (not at scale)
2V
2.5V
2.8V
Reset pulse