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STMicroelectronics Confidential
When PLL1 endures this severe disturbance, it requires some time to recover the proper phase. As
this could entail a visible distortion on top of the screen, the TDA9112 has been provided with a
PLL1 inhibition feature: the two current sources of PLL1 will be turned OFF during the Vsync pulse
and 2 complete lines later. Internal inhibition is activated only by the Vsync pulse extracted from
composite sync.
This features may be disabled through I²C programming (Sad16h/d1).
4.1.9
Frequency Change Speed Limitation
It is well-known that when receiving a new horizontal frequency, PLL1 should not synchronize
immediately with the new frequency, especially when it is lower than the former one. Otherwise the
horizontal scanning transistor would conduct for a longer period of time, while the value of B+ would
not have time to decrease to its newly assigned lower value. This would lead to excessive current
and voltage and possibly destroy the transistor.
In the TDA9112, the PLL1 changing speed has been limited to a safe value.
Warning! This limitation is ineffective when imposing a frequency jump by switching Ro or Co.
4.1.10 PLL2, Duty Factor, ON/OFF
Supposing the oscillator is locked to the Hsync pulse, then PLL2 controls the H scanning transistor
so that the flyback takes place at a definite point on the sawtooth. (Refer to
For this purpose, a positive flyback signal must be sent to pin 12, which is connected to a voltage
comparator with a threshold of one V
BE
, and to the Ground through a 20k
Ω
(typical) resistor. Among
other possibilities, pin 12 may be connected to a secondary of the scanning transformer through a
current-limiting resistor. In order to allow lower values of the limiting resistor, and therefore faster
transmission of the flyback data, the maximum input current into this pin has been increased to
5 mA.
The reference point for PLL2 is the middle of the flyback pulse (as seen on pin 12). PLL2 will
manage to make it coincide with the 4V point on the sawtooth.
PLL2 is a classical charge pump PLL. Its output (pin 5) must be connected to a capacitor as a low-
pass filter. For the entire flyback pulse duration, one of the two 0.15-mA internal current generators
connected to pin 5 will be activated:
●
the source current, when the ramp voltage is lower than 4 V,
●
the sink current, when the ramp voltage is higher than 4 V.
With the flyback pulse centred on the 4V point, the capacitor will receive a null global charge for
each period.
The capacitor value is not critical (22nF for good jitter). With a low capacitor value, PLL2 will more
rapidly recover of any change in the H transistor storage time caused by a black/white video
transition. This will minimize the corresponding distortion of vertical lines.
The Pin 5 voltage directly controls which point on the sawtooth will trigger the scanning transistor
switching OFF. The possible range for pin 5 is between 1.6V and 4V, allowing a transistor storage
time between 0 and:
Similarly, the scanning transistor ON state is triggered when the oscillator sawtooth reaches a
determined voltage; the offset between OFF and ON voltages is constant (adjustable by I²C). As a
result, the TDA9112 will maintain constant duty factor, regardless of PLL2 voltage variations. The
typical Duty factor range is between 30% and 65% and is selected through I²C programming
(Register 00). This is the OFF duty factor, i.e. the ratio of the OFF drive time to the total period.
0.438x T
h
t
flyback
2
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