ST STM32U575I-EV, Руководство пользователя, Страница: 54 / 105

Table 39. Hardware I/O configuration for the comparator interface
I/O Hardware Setting
(1)
Configuration
PB4 SB40
ON PB4 is used as COMP2_INP and connected to JP22 pin1
OFF
PB4 is NOT used as COMP
PB4 can be used for audio MEMS, JTAG, or STMod+
PB5 SB39
ON PB5 is used as COMP2_OUT and connected to TP9
OFF
PB5 is NOT used as COMP
PB5 can be used for USB or STMod+
1. The default configuration is shown in bold.
The input is accessible on pin 1 of the JP22 jumper header. On top of the possibility of routing either the
potentiometer or LDR to PB4, an external source can also be connected to it, using JP22 terminal 1.
The PB5 output of the comparator can be accessed on test point TP9. Refer to the schematic of STM32U575I-EV
Evaluation board.
Table 40 describes the jumper configuration to enable the LDR or the potentiometer to Comp2 function.
Table 40. Jumper configuration to enable the LDR or the potentiometer to Comp2 function
Hardware Setting
(1)
Configuration
JP21 / JP22
JP21[1-2] /
JP22[1-2]
Potentiometer RV1 is routed to pin PB4 of STM32U575AII6Q.
JP21[2-3] /
JP22[1-2]
LDR is routed to pin PB4 of STM32U575AII6Q.
1. The default configuration is shown in bold.
7.20.5 I/O restriction to other features
Caution: Due to the sharing of some I/Os of STM32U575AII6Q by multiple peripherals, the following limitations apply in
using the physical interface features:
•
OPAMP1_VOUT cannot be operated simultaneously with the OCTOSPI_CLK, or the motor
‑
control
functions.
• OPAMP1_INP cannot be operated simultaneously with the STMOD+_ADC, the UCPD IBUS
‑
SENSE or the
motor
‑
control functions.
• COMP cannot be operated simultaneously with the audio MEMS ADF1, the JTAG JRSTN, the STMod+
SPI3_MISO2/MOSI2 and MCU UCPD_DBCC1 functions.
7.21 Analog I/Os, VREF
7.21.1 Description
The STM32U575I-EV Evaluation board provides onboard analog-to-digital ADC and digital-to-analog DAC
converters. The port PA4 can be configured to operate either as ADC input or as DAC output. PA4 is routed
to the CN8 two
‑
way header allowing to fetch signals to or from PA4 or to ground it setting CN8 ON.
7.21.2 ADC/DAC I/O interface
The parameters of the ADC input low
‑
pass filter formed with R143 and C117 can be modified by replacing these
components according to application requirements.
Similarly, parameters of the DAC output low
‑
pass filter formed with R144 and C117 can be modified by replacing
these components according to application requirements.
The VREFP terminal of STM32U575AII6Q is used as the reference voltage for both ADC and DAC. By default, it
is routed to VDDA by setting the JP18 two
‑
way jumper ON. This jumper can be removed and an external voltage
applied to JP18 terminal 2 for specific purposes.
STM32U575I-EV
Analog I/Os, VREF
UM2854 - Rev 1
page 54/105