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Table 19.
ST morpho connector pin assignment
CN11 odd pins
CN11 even pins
CN12 odd pins
CN12 even pins
Pin number
Pin name
Pin number Pin name
Pin number Pin name
Pin number Pin name
1
PC10
2
PC11
1
PC9
2
PC8
3
PC12
4
PD2
3
PB8
4
PC6
5
VDD
6
5V_EXT
5
PB9
6
NC
7
PH3_BOOT0
8
GND
7
8
5V_STLK
9
PF6
10
NC
9
GND
10
PD8
11
PF7
12
IOREF
11
PA5
12
PA12
13
PA13
14
NRST
13
PA6
14
PA11
15
PA14
16
3V3
15
PA7
16
NC
17
PA15
18
5V
17
PB6
18
PB11
19
GND
20
GND
19
PC7
20
GND
21
PB7
22
GND
21
PA9
22
PB2
23
PC13
24
VIN
23
PA8
24
PB1
25
PC14
26
NC
25
PB10
26
PB15
27
PC15
28
PA0
27
PB4
28
PB14
29
PH0
30
PA1
29
PB5
30
PB13
31
PH1
32
PA4
31
PB3
32
AGND
33
VBAT
34
PB0
33
PA10
34
NC
35
PC2
36
PC1
35
PA2
36
PF5
37
PC3
38
PC0
37
PA3
38
PF4
39
PD4
40
PD3
39
GND
40
PE8
41
PD5
42
PG2
41
PD13
42
PF10
43
PD6
44
PG3
43
PD12
44
PE7
45
PD7
46
PE2
45
PD11
46
PD14
47
PE3
48
PE4
47
PE10
48
PD15
49
GND
50
PE5
49
PE12
50
PF14
51
PF1
52
PF2
51
PE14
52
PE9
53
PF0
54
PF8
53
PE15
54
GND
55
PD1
56
PF9
55
PE13
56
PE11
57
PD0
58
PG1
57
PF13
58
PF3
59
PG0
60
GND
59
PF12
60
PF15
61
PE1
62
PE6
61
PG14
62
PF11
63
64
PG15
63
GND
64
PE0
65
PG12
66
PG10
65
PD10
66
67
NC
68
PG13
67
68
69
PD9
70
NC
69
70
1. The default state of BOOT0 is 0. It can be set to 1 when a jumper is plugged on the pins 5-7 of CN11.
2. V
REFP
is not connected to CN12 by default (SB20 OFF).
3. 5V_STLK is the 5V power signal, coming from the STLINK-V3E USB connector. It rises before the 5V signal of the board.
4. PA13 and PA14 are shared with SWD signals connected to STLINK-V3E.
5. PG2 to PG15 can be set to different I/O levels, thanks to the SB to select the source for VDDIO2.
UM2861
CN11 and CN12 ST morpho headers
UM2861
-
Rev 2
page 37/49