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Table 14.
MB1262/CN14 JTAG connector pinout
Board function
Pin
Pin
Board function
Power
1
2
Power
NJTRST
3
4
GND
JTDI
5
6
GND
JTMS/SWDIO
7
8
GND
JTCK/SWCLK
9
10
GND
Pull down
11
12
GND
JTDO/SWO
13
14
GND
NRST
15
16
GND
Pull down
17
18
GND
Pull down
19
20
GND
6.10
DDR3L
Two 16-bit DDR3L NT5CC256M16ER-EK of 4 Gbytes are implemented in flyby topology in MB1263/U6
and U7 positions. They are connected to the dedicated DDR interface of STM32MP157xAA1. For detailed
information concerning the DDR HW design implementation, refer to the application note AN5122 available on the
6.11
eMMC
The STM32MP157xAA1 SDMMC2 in 8-bit wide bus mode drives a THGBMNG5D1LBAIL 32-Gbit eMMC in
MB1263/U5 position.
6.11.1
eMMC I/O interface
describes the HW configuration for the eMMC interface.
Table 15.
HW configuration for the eMMC interface
I/O
Configuration
PB14
SDMMC2_D0 connected to MB1263/U5 DAT0
PB15
SDMMC2_D1 connected to MB1263/U5 DAT1
PB3
SDMMC2_D2 connected to MB1263/U5 DAT2
PB4
SDMMC2_D3 connected to MB1263/U5 DAT3
PA8
SDMMC2_D4 connected to MB1263/U5 DAT4
PA9
SDMMC2_D5 connected to MB1263/U5 DAT5
PE5
SDMMC2_D6 connected to MB1263/U5 DAT6
PD3
SDMMC2_D7 connected to MB1263/U5 DAT7
PE3
SDMMC2_CK connected to MB1263/U5 CLK
PG6
SDMMC2_CMD connected to MB1263/U5 CMD
1. Minimum set of signals required by the boot ROM during eMMC boot in bold
6.12
NAND Flash memory
The STM32MP157xAA1 FMC interface is connected to an 8-Gbit SLC NAND, 8-bit, 8-bit ECC, and 4-KByte PS
MT29F8G08ABACAH4 in MB1262/U11 position.
UM2648
DDR3L
UM2648
-
Rev 2
page 20/61