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ST STM32L496 Series Скачать руководство пользователя страница 3

DocID029937 Rev 2

AN4943

List of tables

3

List of tables

Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FSMC signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

LCD-TFT signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Minimum usable FSMC address bit depending on image size (16 bit RGB565 access) . . 10

Swap operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Содержание STM32L496 Series

Страница 1: ...tination image with a different color format On the STM32L496xx L4A6xx L4Rxxx L4Sxxx microcontrollers the flexible static memory controller FSMC is used to access the LCD TFT display through a paralle...

Страница 2: ...ocontrollers 9 4 Chrom ART Accelerator DMA2D configuration in STM32CubeL4 11 4 1 LCD partial refresh 11 5 New DMA2D features to support Intel 8080 displays 13 5 1 Intel 8080 interface color coding 13...

Страница 3: ...List of tables Table 1 Applicable products 1 Table 2 FSMC signals 7 Table 3 LCD TFT signals 7 Table 4 Minimum usable FSMC address bit depending on image size 16 bit RGB565 access 10 Table 5 Swap oper...

Страница 4: ...c control of LCD TFT display data command by FSMC interface 10 Figure 5 24bpp over 16 bit interface color coding 14 Figure 6 16bpp over 8 bit interface color coding 15 Figure 7 24bpp over 8 bit interf...

Страница 5: ...on www st com STM32L4x6 advanced Arm based 32 bit MCUs reference manual RM0351 STM32L4Rxxx L4Sxxx advanced Arm based 32 bit MCUs reference manual RM0432 Discovery kit with STM32L496AG MCU user manual...

Страница 6: ...dedicated hardware interface The transfer can be done using the CPU the system DMA or using the Chrom ART Accelerator DMA2D In a typical display application example using the STM32L496xx L4A6xx L4Rxxx...

Страница 7: ...The below signals are used to connect the Flexible Static Memory interface FSMC to the LCD TFT display Table 2 FSMC signals Signal name FSMC I O Function A 25 0 O Address bus D 15 0 I O Bidirectional...

Страница 8: ...ontrolled through the physical interface here the FSMC bus using software commands according to the display command set DCS as defined in the MIPI alliance specification for DCS The DCS commands are u...

Страница 9: ...p range for the data transfer When using the DMA2D to access the LCD TFT display on FSMC interface it is important to remember that even if the LCD TFT display target is at a fixed address the Chrom A...

Страница 10: ...he 1st address bit that does not change during the transfer is the bit 16 In this specific case the FSMC_A16 or a higher address bit can be used Table 4 shows the minimum FSMC address bit that can be...

Страница 11: ...IXEL_WIDTH LAYER_SIZE_X 2 ST7789H2_LCD_PIXEL_HEIGHT LAYER_SIZE_Y 2 LAYER_SIZE_X LAYER_SIZE_Y 2 DMA2D configuration DMA2D_Config 3 Start DMA2D transfer hal_status HAL_DMA2D_Start_IT Dma2dHandle uint32_...

Страница 12: ...ffset 0x0 No offset in input Dma2dHandle LayerCfg 1 RedBlueSwap DMA2D_RB_REGULAR No R B swap for the input foreground image Dma2dHandle LayerCfg 1 AlphaInverted DMA2D_REGULAR_ALPHA No alpha inversion...

Страница 13: ...coding which requires the most significant byte to be transmitted first red component in case of the RGB888 pixel format This mismatch requires extra byte reordering steps to get the right byte order...

Страница 14: ...red 16bpp 64k colors over 8 bit interface Figure 6 shows the pixel color coding for 16bpp displays over an 8 bit bus interface MSv48347V1 B0 7 B0 6 B0 5 B0 4 B0 3 B0 2 B0 1 B0 0 G0 7 G0 6 G0 5 G0 4 G0...

Страница 15: ...ost significant bits of the bus D 7 2 and data lines D0 and D1 are ignored MSv48348V1 1 2 3 4 Transfer number D7 D6 D5 D4 D3 D2 D1 D0 R0 4 R0 3 R0 2 R0 1 R0 0 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B...

Страница 16: ...A2D_OPFCCR register This feature exists on the STM32L4 Series and STM32L4 Plus Series 5 2 2 Byte swap The MSB and the LSB bytes of a half word are swapped in the output FIFO This is done by setting th...

Страница 17: ...the FSMC D 7 0 lines and the display D 7 0 lines are connected to the FSMC D 15 8 lines MSv48350V1 B0 7 B0 6 B0 5 B0 4 B0 3 B0 2 B0 1 B0 0 G0 7 G0 6 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 R0 7 R0 6 R0 5 R0 4 R...

Страница 18: ...s B0 7 B0 6 B0 5 B0 4 B0 3 B0 2 B0 1 B0 0 G0 7 G0 6 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 R0 7 R0 6 R0 5 R0 4 R0 3 R0 2 R0 1 R0 0 1 2 3 4 Transfer number R1 7 R1 6 R1 5 R1 4 R1 3 R1 2 R1 1 R1 0 B0 7 B0 6 B0 5...

Страница 19: ...el 1 8 bit FSMC data bus 1 2 3 4 Transfer number D7 D6 D5 D4 D3 D2 D1 D0 R0 4 R0 3 R0 2 R0 1 R0 0 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 R1 4 R1 3 R1 2 R1 1 R1 0 G1 5 G1 4 G1 3 G1 2 G1...

Страница 20: ...out using the CPU or the DMA resources A focus is given to the correct control of the Data command control signal of the LCD TFT display Some code examples have also been provided to setup the Chrom A...

Страница 21: ...ry 21 7 Revision history Table 6 Document revision history Date Revision Changes 27 Jan 2017 1 Initial release 23 Oct 2017 2 Added STM32L4Rxxx L4Sxxx devices in the whole document Added Section 5 New...

Страница 22: ...sers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to...

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