CAN bootloader
AN2662
Doc ID 14156 Rev 1
Next, the code initializes the serial interface accordingly. Using this calculated baud rate, an
acknowledge byte
(0x79)
is returned to the host, which signals that the STM32F105xx and
STM32F107xx is ready to receive user commands.
3.2 CAN
settings
The STM32F105xx and STM32F107xx CAN2 is compliant with the 2.0A and B (active)
specifications with a bitrate up to 1Mbit/s. It can receive and transmit standard frames with
11-bit identifiers as well as extended frames with 29-bit identifiers.
shows a CAN frame that uses the standard identifier only.
Figure 27.
CAN frame
In this application, the CAN 2 settings are
●
Standard identifier (not extended)
●
Bit rate: At the beginning it is 125 kbps; during run time it can be changed via the speed
command to achieve a maximum bit rate of 1 Mbps.
The transmit settings (from STM32F105xx and STM32F107xx to the host) are:
●
Tx mailbox0: On
●
Tx mailbox1 and Tx mailbox2: Off
●
Tx identifier: (0x00, 0x01, 0x02, v03, 0x11, 0x21, 0x31, 0x43, 0x63, 0x73, 0x82, 0x92).
The receive settings (from the host to STM32F105xx and STM32F107xx ) are:
●
Synchronization byte, 0x79, is in the RX identifier and not in the data field.
●
RX identifier depends on the command (0x00, 0x01, 0x02, 0x03, 0x11, 0x21, 0x31,
0x43, 0x63, 0x73, 0x82, 0x92).
●
Error checking: If the error field (bit [6:4] in the CAN_ESR register) is different from
000b, the message is discarded and a NACK is sent to the host.
●
In FIFO overrun condition, the message is discarded and a NACK is sent to the host.
●
Incoming messages can contain from 1 to 8 data bytes.
The CAN2 peripheral is accessible via pins PB6 (TX) and PB5 (RX)
Note:
CAN1 is clocked during CAN bootloader execution because in STM32F105xx and
STM32F107xx CAN1 manages the communication between CAN2 and SRAM.
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