
High-definition multimedia interface, consumer electronics control (HDMI-CEC)
AN3127
Doc ID 16896 Rev 2
Figure 7.
Addresses within a HDMI cluster
1.4.2 Enhanced
DDC
The enhanced DDC described in this section is defined in VESA “ENHANCED DISPLAY
DATA CHANNEL STANDARD Version 1 (September 2, 1999)”. All sinks are required to
support these enhanced DDC features. If the E-EDID structure of a sink is longer than 256
bytes, it should support the segment pointer.
Timing
Data is synchronized with the SCL signal and timing should comply with the Standard Mode
of the I2C specification (100 kHz maximum clock rate).
The I2C bus is a standard two-wire (clock and data) serial databus protocol. Refer to the I2C
specification for details.
Note that a HDMI sink may hold off the DDC transaction by stretching the SCL line during
the SCL-low period following the Acknowledge bit as permitted by the I2C specification. All
HDMI sources should delay the DDC transaction while the SCL line is being held low.
Data transfer protocols
The source should use I2C commands to read information from a sink’s E-EDID with a slave
address.
In Enhanced DDC, a segment pointer is used to address the E-EDID outside the 256 bytes
normally addressable by the 0xA0/0xA1 addresses. The Enhanced DDC protocol sets the
segment pointer before the remainder of the DDC command.