ST STM32303C-EVAL, Руководство пользователя

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UM1590 Running the demonstration
Doc ID 023892 Rev 1 17/65
2.2 Clock sources
2.2.1 Clock control
The STM32F30x/31x internal clocks are derived from the HSE (clocked by the external
8 MHz crystal).
In this demonstration application, the various system clocks are configured as follows:
●
System clock is set to 72 MHz: the PLL is used as the system clock source: 72 MHz.
● HCLK frequency is set to 72 MHz.
●
Timer clock (TIMCLK) is set to 72 MHz.
● PCLK1 is set to 36 MHz.
●
PCLK2 is set to 72 MHz.
Only the RTC is clocked by a 32 kHz external oscillator.
Figure 11 illustrates the clock tree organization for this demo.
Figure 11. Clock tree diagram
MS31110V2
RTC
LSE
32768Hz
APB1 prescaler
/2
APB2 prescaler
/1
72MHz
36MHz
AHB prescaler
/1
PLL multiplicator
x9
HSE RC
8MHz
HCLK 72 MHz to AHB bus,
core, memory and DMA
SYSCLK
72MHz