Figure 9.
Example of SCR leakage current (Tj = 125°C)
The evaluation board solution is low side bypass topology: the
SCR gate driver is implemented with
connected in series to the SCR gates. This solution allows controlling only the SCR
positively biased without sensing the polarity of the AC line signal.
Assume the PFC output capacitor is already charged and the PFC is in normal operation. Consider the AC
positive half sine wave. Also consider that Q1 is on with 50 mA pulsed gate current, thanks to the EN 5 V PWM
signal (10 kHz, α = 0.1, for instance). Thus, the positively biased SCR X1 is turned on. The nominal current flows
through the D3 diode, the PFC output stage, and X1.
During this AC positive half sine wave, D2 cathode to anode voltage is negative (V
AK_D2
< 0), D2 diode is
blocked. No current can flow through the X2 gate and, consequently, the SCR X2 remains blocked as long as it is
reversed biased.
Thanks to the SCR gate driver topology, the nonconducting SCR gate cannot be supplied. In fact, its series diode
is blocked. Thus, no more reverse losses are added. D1 and D2 automatically switch the gate current to the
positively biased SCR. This explains why no polarity sense is required and no reverse conduction can occur.
Figure 10.
SCR gate driver operation
UM2948
SCR gate driver with automatic switching operation
UM2948
-
Rev 1
page 8/28
