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UM

101

5

Schematics

Doc 

ID
 1

8124

 R
e

v 

1

2

3

/38

Figure 6.

DDR interface schematic

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

4

4

3

3

2

2

1

1

Spear300

CPU Board

2.3

DDR2 interface

2

8

20 Oct 2009

Place close to pin

Place close to pin

Place close to pin

Place close to pin

Place close to DDR2 Chip

Place close to DDR2 Chip

Place close to LAST DDR2 Chip

Place close to pins

nCAS

nCS0

DQS0

DQS1

DQM0
DQM1

BA0
BA1
BA2

CLK_EN

CLK

nCLK

nCS0

nDQS0

nDQS1

nRAS

nWE

ODT0

ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9

VREF

ODT0

DATA0
DATA1
DATA2
DATA3

DATA5

DATA9

DATA7

ADDR10
ADDR11
ADDR12
ADDR13

DATA4

DATA6

DATA11

DATA15

DATA13

DATA10

DATA8

DATA14

DATA12

DATA6

DATA15

DATA10

DATA11

DATA2

DATA12

DATA7

DATA4

DATA8

DATA9

DATA1

DATA0

DATA13

DATA14

DATA3

DATA5

ADDR1

ADDR3
ADDR4
ADDR5
ADDR6

ADDR11

ADDR7

ADDR12

ADDR8

ADDR13

ADDR9

ADDR0

ADDR10

ADDR2

BA2
BA1
BA0

nCS1
nWE

nCAS

nRAS

nCLK

CLK_EN
CLK

ODT1

DQS1
nDQS1

nDQS0

DQS0

DQM0
DQM1

nCLK

VREF

CLK

DATA7

DATA10

DATA15

DATA14

DATA1

DATA9

DATA6

DATA5

DATA13

DATA12

DATA2

DATA3

DATA8

DATA11

DATA0

DATA4

ADDR1

ADDR3
ADDR4
ADDR5
ADDR6

ADDR11

ADDR7

ADDR12

ADDR8

ADDR13

ADDR9

ADDR0

ADDR10

ADDR2

BA2
BA1
BA0

nWE

nCAS

nRAS

nCLK

CLK_EN
CLK

DQS1
nDQS1

nDQS0

DQS0

DQM0
DQM1

nCS1

ODT1

DATA[0..15]

ADDR[0..13]

VREF

VREF

VREF

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

1.8V_SP

Rev

Date:

Sheet

of

Board

Title

Code

Project

Rev

Date:

Sheet

of

Board

Title

Code

Project

Rev

Date:

Sheet

of

Board

Title

Code

Project

C7

0.

1 uF

 X5R

 10V

C7

0.

1 uF

 X5R

 10V

C19

0.

1 uF

 X5R

 10V

C19

0.

1 uF

 X5R

 10V

C62
10 uF X5R 10V

C62
10 uF X5R 10V

R9
470 Ohm

R9
470 Ohm

M

IC

R

ON DDR

2

8

M

B

x16 M

T

47H64M

16HR

-3

U2

MT47H64M16HR3,NC

M

IC

R

ON DDR

2

8

M

B

x16 M

T

47H64M

16HR

-3

U2

MT47H64M16HR3,NC

DATA0

G8

DATA1

G2

DATA2

H7

DATA3

H3

DATA4

H1

DATA5

H9

DATA6

F1

DATA7

F9

DATA8

C8

DATA9

C2

DATA10

D7

DATA11

D3

DATA12

D1

DATA13

D9

DATA14

B1

DATA15

B9

ADDR0

M8

ADDR1

M3

ADDR2

M7

ADDR3

N2

ADDR4

N8

ADDR5

N3

ADDR6

N7

ADDR7

P2

ADDR8

P8

ADDR9

P3

ADDR10

M2

ADDR11

P7

ADDR12

R2

ADDR13

R8

UDM

B3

LDM

F3

VREF

J2

CKE

K2

nWE

K3

BA0

L2

BA1

L3

BA2

L1

nUDQS

A8

UDQS

B7

nLDQS

E8

LDQS

F7

CLK

J8

nCLK

K8

nRAS

K7

nCAS

L7

nCS

L8

ODT

K9

RFU2

R7

RFU1

R3

NC2

A2

NC1

E2

VDD1V8_1

A1

VDD1V8_2

E1

VDD1V8_3

M9

VDD1V8_4

R1

VDD1V8_5

J9

VDDL1V8

J1

VDDQ1V8_1

A9

VDDQ1V8_2

C1

VDDQ1V8_3

C3

VDDQ1V8_4

C7

VDDQ1V8_5

C9

VDDQ1V8_7

G1

VDDQ1V8_8

G3

VDDQ1V8_9

G7

VDDQ1V8_10

G9

VSS5

A3

VSS4

E3

VSS3

J3

VSS2

N1

VSS1

P9

VSSDL

J7

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VDDQ1V8_6

E9

C10

0.

1 uF

 X5R

 10V

C10

0.

1 uF

 X5R

 10V

C8

0.

1 uF

 X5R

 10V

C8

0.

1 uF

 X5R

 10V

R2
100 Ohm

R2
100 Ohm

C13

0.

1 uF

 X5R

 10V

C13

0.

1 uF

 X5R

 10V

R1

121 Kohm 1%

R1

121 Kohm 1%

C12

0.

1 uF

 X5R

 10V

C12

0.

1 uF

 X5R

 10V

REF7

FIDUCIAL

REF7

FIDUCIAL

C1

0.

1 uF

 X5R

 10V

C1

0.

1 uF

 X5R

 10V

R5
100 Ohm

R5
100 Ohm

C14

0.

1 uF

 X5R

 10V

C14

0.

1 uF

 X5R

 10V

REF8

FIDUCIAL

REF8

FIDUCIAL

C11

0.

1 uF

 X5R

 10V

C11

0.

1 uF

 X5R

 10V

R3
100 Ohm

R3
100 Ohm

C15

0.

1 uF

 X5R

 10V

C15

0.

1 uF

 X5R

 10V

C20

0.

1 uF

 X5R

 10V

C20

0.

1 uF

 X5R

 10V

REF1

FIDUCIAL

REF1

FIDUCIAL

C6

0.

1 uF

 X5R

 10V

C6

0.

1 uF

 X5R

 10V

TP30

TP_diff

TP30

TP_diff

1

1

2

2

C16

0.

1 uF

 X5R

 10V

C16

0.

1 uF

 X5R

 10V

C2

0.1 uF X5R 10V

C2

0.1 uF X5R 10V

REF2

FIDUCIAL

REF2

FIDUCIAL

R4
100 Ohm

R4
100 Ohm

C18

0.

1 uF

 X5R

 10V

C18

0.

1 uF

 X5R

 10V

C4
0.1 uF X5R 10V

C4
0.1 uF X5R 10V

M

IC

R

ON DDR

2

8

M

B

x16 M

T

47H64M

16HR

-3

U3

MT47H64M16HR3

M

IC

R

ON DDR

2

8

M

B

x16 M

T

47H64M

16HR

-3

U3

MT47H64M16HR3

DATA0

G8

DATA1

G2

DATA2

H7

DATA3

H3

DATA4

H1

DATA5

H9

DATA6

F1

DATA7

F9

DATA8

C8

DATA9

C2

DATA10

D7

DATA11

D3

DATA12

D1

DATA13

D9

DATA14

B1

DATA15

B9

ADDR0

M8

ADDR1

M3

ADDR2

M7

ADDR3

N2

ADDR4

N8

ADDR5

N3

ADDR6

N7

ADDR7

P2

ADDR8

P8

ADDR9

P3

ADDR10

M2

ADDR11

P7

ADDR12

R2

ADDR13

R8

UDM

B3

LDM

F3

VREF

J2

CKE

K2

nWE

K3

BA0

L2

BA1

L3

BA2

L1

nUDQS

A8

UDQS

B7

nLDQS

E8

LDQS

F7

CLK

J8

nCLK

K8

nRAS

K7

nCAS

L7

nCS

L8

ODT

K9

RFU2

R7

RFU1

R3

NC2

A2

NC1

E2

VDD1V8_1

A1

VDD1V8_2

E1

VDD1V8_3

M9

VDD1V8_4

R1

VDD1V8_5

J9

VDDL1V8

J1

VDDQ1V8_1

A9

VDDQ1V8_2

C1

VDDQ1V8_3

C3

VDDQ1V8_4

C7

VDDQ1V8_5

C9

VDDQ1V8_7

G1

VDDQ1V8_8

G3

VDDQ1V8_9

G7

VDDQ1V8_10

G9

VSS5

A3

VSS4

E3

VSS3

J3

VSS2

N1

VSS1

P9

VSSDL

J7

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VDDQ1V8_6

E9

C5

0.

1 uF

 X5R

 10V

C5

0.

1 uF

 X5R

 10V

S

p

ear300

DDR2 Interface

U1B

Spear300

S

p

ear300

DDR2 Interface

U1B

Spear300

DATA0

P11

DATA1

R11

DATA2

T11

DATA3

U11

DATA4

T12

DATA5

R12

DATA6

P12

DATA7

P13

DATA8

T17

DATA9

T16

DATA10

U17

DATA11

U16

DATA12

U14

DATA13

U13

DATA14

T13

DATA15

R13

ADDR0

T2

ADDR1

T1

ADDR2

U1

ADDR3

U2

ADDR4

U3

ADDR5

U4

ADDR6

U5

ADDR7

T5

ADDR8

R5

ADDR9

P5

ADDR10

P6

ADDR11

R6

ADDR12

T6

ADDR13

U6

ADDR14

R7

nRAS

U8

nCAS

T8

nWE

T7

nCS0

P9

nCS1

R9

DQS0

U10

nDQS0

T10

nDQS1

T15

DQS1

U15

ODT0

T3

ODT1

T4

GATE_OPEN0

R10

GATE_OPEN1

R14

DQM0

U12

DQM1

T14

BA0

P7

BA1

P8

BA2

R8

CLK

T9

nCLK

U9

CLK_EN

U7

VREF

P10

COMP_2V5_REXT

P4

COMP_2V5_GND

R4

C17

0.

1 uF

 X5R

 10V

C17

0.

1 uF

 X5R

 10V

R8
470 Ohm

R8
470 Ohm

C3

0.

1 uF

 X5R

 10V

C3

0.

1 uF

 X5R

 10V

C9

0.

1 uF

 X5R

 10V

C9

0.

1 uF

 X5R

 10V

C99

0.1 uF X5R 10V

C99

0.1 uF X5R 10V

C61
10 uF X5R 10V

C61
10 uF X5R 10V

FB1

WUR

T

H 742792023

FB1

WUR

T

H 742792023

FB2

WUR

T

H 742792023

FB2

WUR

T

H 742792023

Содержание SPEAr320

Страница 1: ...EVALSPEAr320CPU SPEAr320 CPU evaluation board UM1015 User manual Doc ID 18124 Rev 1 October 2010 www st com STMicroelectronics...

Страница 2: ...BLANK...

Страница 3: ...20 microprocessors the evaluation board kit comprises one board one serial cable interface and one power supply CPU board features SPEAr320 embedded MPU Up to 2 Gbit DDR2 333 MHz standard 128 Mbytes U...

Страница 4: ...k diagram 8 3 Expansion connectors 11 4 Switch and jumper settings 15 4 1 Switch 1 settings 15 4 2 Switch 2 settings 16 4 3 Jumpers and connectors 17 5 Board components 18 6 Schematics 22 7 Board layo...

Страница 5: ...rd extension connector J12 11 Table 3 CPU board extension connector J13 13 Table 4 Switch 1 SoC functional configuration 15 Table 5 Switch 1 debug configuration 15 Table 6 Switch 1 functional configur...

Страница 6: ...2 Figure 6 DDR interface schematic 23 Figure 7 USB interface schematic 24 Figure 8 USB power and optional part schematic 25 Figure 9 Miscellaneous interfaces schematic 26 Figure 10 Power supply schema...

Страница 7: ...connector J17 serial link to a host PC 2 On the host PC running Windows or Linux start the Terminal program 3 Connect the 5 V voltage adapter supplied in the EVALSPEAR320CPU package to the J11 power v...

Страница 8: ...ts size is 128 Mbits x 8 16 Mbits x 8 x 8 banks Local power supply The local power supply is based on a monolithic voltage regulator for the chip set and DDR2 3 PM6641 It is generated locally in order...

Страница 9: ...tion in case of a short circuit in the USB cable Device port The board has one USB 2 0 device port 2 0 4 Debug interface The JTAG interface can be used for static debugging which means that it is poss...

Страница 10: ...generates all the required voltages as follows 1 2V Switching regulator PM6641 to supply the internal logic of the SPEAr320 MPU 1 8V Switching regulator PM6641 for the DDR2 memory 2 5V LDO regulator f...

Страница 11: ...h hole pins 10 pins are connected to GND Figure 4 86 pin connectors J12 and J13 Table 2 CPU board extension connector J12 Pin Description Pin Description 1 1 8V 2 5V 3 1 8V 4 5V 5 1 8V 6 5V 7 1 8V 8 5...

Страница 12: ...2V 65 PL_GPIO7 66 1 2V 67 PL_GPIO1 68 1 2V 69 PL_GPIO0 70 3 3V 71 NC 72 3 3V 73 NC 74 3 3V 75 NC 76 3 3V 77 GND 5 78 GND 5 79 80 81 82 83 84 85 86 1 If J20 Jumper is set to pin2 3 otherwise NC 2 If J2...

Страница 13: ...21 PL_GPIO60 22 PL_GPIO67 23 PL_GPIO65 24 PL_GPIO71 25 PL_GPIO62 26 PL_GPIO75 27 PL_GPIO68 28 PL_GPIO82 29 PL_GPIO52 30 PL_GPIO76 31 PL_GPIO53 32 PL_GPIO85 33 PL_GPIO51 34 PL_GPIO87 35 PL_GPIO54 36 P...

Страница 14: ...74 GND 75 PL_CLK1 76 ADC VREFP 77 GND 1 78 GND 1 79 80 81 82 83 84 85 86 1 Physically connected to the internal metal plane of the connector Pins 77 through 81 and 82 through 86 are shorted together T...

Страница 15: ...tion 3 For other configurations refer to the SPEAr320 user manual available at www st com spear Table 4 Switch 1 SoC functional configuration Bit Description 1 Test see Debug configuration below 2 Res...

Страница 16: ...invalid condition Table 7 Switch 2 settings Boot from SW2 1 SW2 2 SW2 3 SW2 4 SW2 5 SW2 6 SW2 7 SW2 8 USB_BOOT Off On Off On Off On Off On ETH parameter from I2C ROM On Off Off On Off On Off On ETH p...

Страница 17: ...different types of RS 232 cables a Two pins are connected to the ST3232 Receive Transmit side Two pins are connected to the RS 232 Receive Transmit connector side Connector J17 is a connector for stan...

Страница 18: ...9 C50 C56 C57 C58 C59 C60 C99 C100 C101 C102 0402 Ceramic capacitor 0 1uF 10 10V X5R 0402 Resistor R42 R43 R44 R45 R46 R47 R48 R50 0603 Resistor 0603 0 ohm Resistor R30 R31 R32 R33 R34 R35 R36 R37 R38...

Страница 19: ...lator Y2 RAD HC49 Crystal Oscillator 24MHz 30ppm through hole Resistor R70 0603 Resistor 0603 27k ohm 1 0 1W Crystal oscillator Y1 XT38T Crystal Oscillator 32 768KHz 20ppm d2x6mm Capacitor C92 0603 Ce...

Страница 20: ...Surface mount 8 way micro dip switch pitch1 27mm Ferrite bead FB8 FB9 FB12 FB13 FB14 FB15 FB10 FB16 0603 Ferrite 2506033007Y0 SMD 400mA LED D5 D6 D7 D8 D9 0805P LED SMD 2 0 x 1 25mm Superbright Green...

Страница 21: ...PM6641 STm DDR2 3 Voltage Regulator 48pin VFQFPN Connector J5 J6 J7 J8 J9 2X1 2 54 MD STRIP 2X1 2 54 MD Strip vertical male 2X1 2 54mm Connector J22 2X2 2 54 MD STRIP 2X2 2 54 MD Strip vertical male 2...

Страница 22: ...ed boot options 07 Daughterboard and UART connectors PL_GPIO 0 97 PL_CLK 1 4 AIN 0 7 ADC_VREFP ADC_VREFN VREF INRESET nRESET 03 USB Interface SchDoc 03 USB Interface 06 PL_GPIO SchDoc 06 PL_GPIO PL_GP...

Страница 23: ...F2 VSSQ8 F8 VSSQ9 H2 VSSQ10 H8 VDDQ1V8_6 E9 C10 0 1 uF X5R 10V C10 0 1 uF X5R 10V C8 0 1 uF X5R 10V C8 0 1 uF X5R 10V R2 100 Ohm R2 100 Ohm C13 0 1 uF X5R 10V C13 0 1 uF X5R 10V R1 121 Kohm 1 R1 121 K...

Страница 24: ...M1 USB_HOST0_VBUS J3 USB_HOST0_DM K2 USB_HOST0_DP K1 USB_HOST1_VBUS H3 USB_HOST1_DM H2 USB_HOST1_DP H1 USB_HOST1_OVERCUR J4 USB_HOST0_OVERCUR H4 USB_TXR_TUNE K5 USB_ANALOG_TEST L4 USB_DEV_VDD3V3 N3 U...

Страница 25: ...e C102 close to U13 5 VBus Place C101 close to U14 5 VBus Place C100 close to U15 5 Vbus HOST0_INF_DM HOST1_INF_DP USB_DEV_DM USB_DEV_DP USB_DEV_5V USB_DEV_INF_DM USB_DEV_INF_DP HOST0_INF_DP HOST0_DM...

Страница 26: ...m R14 10 Kohm R15 10 Kohm R15 10 Kohm FB12 FERRITE FB12 FERRITE R34 1 Kohm R34 1 Kohm GND Y1 32 768Khz GND Y1 32 768Khz C28 0 1 uF X5R 10V C28 0 1 uF X5R 10V A1 A2 K D3 D BAV70 A1 A2 K D3 D BAV70 R45...

Страница 27: ...Ohm R6 100 Ohm R46 0 Ohm R46 0 Ohm L3 1 uH 1 7A L3 1 uH 1 7A A K G D4 SCR TS420 B_1 A K G D4 SCR TS420 B_1 PD1 PADX2 80H60 PD1 PADX2 80H60 1 2 R61 75 Kohm R61 75 Kohm C73 10 uF X5R 10V C73 10 uF X5R...

Страница 28: ...3_9 K12 VDD3V3_10 L12 VDD3V3_11 M12 DDR_VDD1V8_1 M5 DDR_VDD1V8_2 N5 DDR_VDD1V8_3 N6 DDR_VDD1V8_4 N7 DDR_VDD1V8_5 N8 DDR_VDD1V8_6 N9 DDR_VDD1V8_7 N10 DDR_VDD1V8_8 N11 GND_1 G6 GND_2 G7 GND_3 G8 GND_4 G...

Страница 29: ...AMTEC MIS 038 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34...

Страница 30: ...o GND 03 July 2009 Add GND to C94 C95 C96 C97 1 5 FB8 is only connected to PIN 6 of J1 at Page3 Add a FB16 FB16 is connected to PIN 5 of J1 at Page3 FB9 is connected to PIN 9 and PIN 11 of J2 at Page3...

Страница 31: ...layout Figure 14 SPEAr320 CPU evaluation board layout top view Figure 15 SPEAr320 CPU evaluation board layout bottom view JTAG J3 JTAG J3 USB device J1 USB host J2 Serial link J17 Power J11 Reset butt...

Страница 32: ...ision 2 0 SPEAr320 CPU evaluation boards are documented in revision 1 of the EVALSPEAr320CPU user manual Earlier board revisions are documented in UM0842 the EVALSPEAr320PLC user manual 8 2 Document r...

Страница 33: ...tion software or related documentation or modify reverse engineer de compile or disassemble the demonstration software in whole or in part You warrant to ST that the Demo Product will be used and mana...

Страница 34: ...provisions had not been inserted in this Agreement WAIVER The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a s...

Страница 35: ...hts notices included on or embedded in the Licensed Software You agree to prevent any unauthorized copying of the Licensed Software and related documentation RESTRICTIONS Unless otherwise explicitly s...

Страница 36: ...tion or warranty by ST or alter this disclaimer or warranty and in no additional obligations or liabilities shall arise from ST s providing such information or services ST does not assume or authorize...

Страница 37: ...not been inserted in this Agreement WAIVER The waiver by either party of any breach of any provisions of this Agreement shall not operate or be construed as a waiver of any other or a subsequent breac...

Страница 38: ...ARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLE...

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