
8
Schematics
Figure 12.
Power and decoupling
5.0V_SR
3.3V_SR
1.25V_SR
5.0V_LR
5.0V_SR
3.3V_SR
1.25V_SR
VDD_HV_IO_MAIN
VDD_HV_IO_JTAG/VDD_HV_OSC
VDD_HV_IO_ETH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
AGND
AGND
NOT MOUNTED
NOT MOUNTED
NOT MOUNTED
AGND
RING -HEADED FOR PROBE HOOK
1-2 CLOSED
DEFAULT
1-2 CLOSED
DEFAULT
1-2 CLOSED
DEFAULT
1-2 CLOSED
DEFAULT
default OPEN
ADC
OSC & JTAG (3.3V or 5V)
I/O (3.3v - 5V)
FLASH DECOUPLING
MCU CORE LOGIC (1.25V)
SPC572LADPT100S
Power Pins
VSS_HV_ADR
28
VDD_HV_ADR
29
VDD_HV_ADV
39
VDD_HV_IO_JTAG/VDD_HV_OSC
55
VDD_HV_IO_MAIN3
85
VDD_HV_IO_MAIN2
51
VDD_HV_IO_MAIN1
20
VDD_HV_FLA
86
VDD_LV3
68
VDD_LV2
52
VDD_LV1
19
EPAD
103
VDD_HV_IO_ETH
95
ETHERNET SUPPLY
DUT1A
LAVAREDO-LQFP100EP
1
2
3
4
1437671-6
J2
0R
1/10W
0603
R2
TEST2
GT1
TEST2
GT2
TEST2
GT3
TEST2
GT4
TEST2
GT5
TEST2
TP1
49R9
1/10W
0805
R1
STRIP2PM
J8
2
1
3
STRIP3PM
J3
2
1
3
STRIP3PM
J5
2
1
3
STRIP3PM
J6
2
1
3
STRIP3PM
J7
0805
2.2uF
16V
X7R
C1
0603
100nF
50V
X7R
C2
0603
1nF
100V
X7R
C3
0805
4.7uF
16V
X7R
C4
0603
100nF
50V
X7R
C5
0603
1nF
100V
X7R
C6
0805
4.7uF
16V
X7R
C7
0603
100nF
50V
X7R
C8
0603
1nF
100V
X7R
C9
0603
100nF
50V
X7R
C10
0603
100nF
50V
X7R
C13
0603
100nF
50V
X7R
C16
0603
1nF
100V
X7R
C11
0603
1nF
100V
X7R
C14
0603
1nF
100V
X7R
C17
0805
4.7uF
16V
X7R
C15
0805
4.7uF
16V
X7R
C18
0805
4.7uF
16V
X7R
C12
0603
100nF
50V
X7R
C19
0603
1nF
100V
X7R
C20
0805
4.7uF
16V
X7R
C21
0805
2.2uF
16V
X7R
C25
0603
100nF
50V
X7R
C26
0603
1nF
100V
X7R
C27
0805
2.2uF DNP
16V
X7R
C28
0603
100nF
50V
X7R
C29
0603
1nF
100V
X7R
C30
0805
2.2uF DNP
16V
X7R
C31
0603
100nF
50V
X7R
C32
0603
1nF
100V
X7R
C33
0805
2.2uF DNP
16V
X7R
C24
0603
100nF
50V
X7R
C22
0603
47nF
50V
X7R
C23
GND
AGND
VDD_HV_ADV
VDD_HV_ADR
VDD_HV_FLA
default OPEN
STRIP2PM
J25
default OPEN
STRIP2PM
J26
VDD_LV1
VDD_LV2
VDD_LV3
GND
1-2 CLOSED
DEFAULT
2
1
3
STRIP3PM
J1
5.0V_LR
VDD_LV3
VDD_HV_IO_JTAG/VDD_HV_OSC
VDD_HV_IO_MAIN
VDD_HV_IO_ETH
UM3063
-
Rev 1
page 21/29
UM3063
Schematics