DocID025978 Rev 1
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AN4450
Using FIFO modes
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5.2
Extra FIFO modes
For all the following modes the trigger signal is the IA bit[2] of register INT_SOURCE (0x25)
which is configured by register INTERRUPT_CFG (0x24).
5.2.1
Stream to FIFO mode (F_MODE[2..0]="011" in FIFO_CTRL (0x2E))
The FIFO works in Stream mode till a trigger event occurs, then it changes to FIFO mode.
5.2.2
Bypass to Stream mode (F_MODE[2..0]="100" in FIFO_CTRL (0x2E))
The FIFO is in Bypass mode, so it stays empty because it is not operational, till a trigger
event occurs, then the FIFO enters in Stream mode.
5.2.3
Bypass to FIFO mode (F_MODE[2..0]="111" in FIFO_CTRL (0x2E))
The FIFO is in Bypass mode, so it stays empty because it is not operational, till a trigger
event occurs, then the FIFO mode starts.
