ST 32F412GDISCOVERY, Руководство пользователя

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UM2032 Rev 3 21/40
UM2032 Hardware layout and configuration
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5.7 Boot options
After reset, the STM32F412ZGT6 boots from the following embedded memory locations
depending on bits BOOT0 and BOOT1 (see
Table 5 ):
•
User Flash memory (non-protected)
•
System Flash memory (protected) for In Circuit Programming
•
RAM for debugging
BOOT0 is set by the input pin BOOT0 of the STM32F412ZGT6. Its level is set by default to
0 by closing the solder bridge SB31 and keeping R69 unfitted. BOOT1 is shared with the
GPIO PB2 used as QSPI_CLK and is sampled by the STM32F412ZGT6 only at RESET
phase. At start-up, BOOT1 level depends on the resistors R104 and R100. By default R100
and R104 are not fitted on the Discovery kit to avoid any influence on the QSPI_CLK signal
using same pin as BOOT1.
The application note “ STM32 microcontroller system memory boot mode” Application note
(AN2606) details the bootloader mechanism and configurations.
Boot-related solder bridge and resistor settings are reported in Table 6 :
Table 5. Boot options
BOOT0 BOOT1 Boot Memory
0 X User Flash
1 0 System Flash
1 1 RAM
Table 6. Boot-related solder bridge and resistor settings
Resistors, solder bridge Description
SB31 ON
R69 not fitted
BOOT0=0
R100 and
R104 not fitted
BOOT1=X
Default Setting
Microcontroller STM32F412ZGT6 boots from user Flash memory.
SB31 OFF
R69 fitted
(any value
from 0 to 10K)
BOOT0=1
R100 not fitted
R104 fitted
(1)
BOOT1=0
1. To keep Quad-SPI functionality after boot-up phase, the user should select a resistor value of R100 or
R104 insuring a weak pull-down or weak pull-up respectively.
Microcontroller STM32F412ZGT6 boots from system Flash.
R104 is a pull-down resistor on PB2 shared between BOOT1 and
QSPI_CLK.
R100 fitted
(1)
R104 not fitted
BOOT1=1
Microcontroller STM32F412ZGT6 from RAM.
R100 is a pull-up resistor on PB2 shared between BOOT1 and
QSPI_CLK.