SSV IGW/100, Справочник по аппаратуре

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IGW/100 – Appendix 1: Pin Assignment – 128-Pin QIL Connector
S S V E MB E DD E D S Y ST EM S
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APPENDIX 1: PIN ASSIGNMENT – 128-PIN QIL CONNECTOR
A1.1 Pin Assignment – 128-pin QIL Connector (1. Part)
Pin Name Group Function
1 PA0 PIO Parallel I/O, port A, bit 0*
2 PA1 PIO Parallel I/O, port A, bit 1*
3 PA2 PIO Parallel I/O, port A, bit 2*
4 PA3 PIO Parallel I/O, port A, bit 3*
5 PA4 PIO Parallel I/O, port A, bit 4*
6 PA5 PIO Parallel I/O, port A, bit 5*
7 PA6 PIO Parallel I/O, port A, bit 6*
8 PA7 PIO Parallel I/O, port A, bit 7*
9 PB0 PIO Parallel I/O, port B, bit 0*
10 PB1 PIO Parallel I/O, port B, bit 1*
11 PB2 PIO Parallel I/O, port B, bit 2*
12 PB3 PIO Parallel I/O, port B, bit 3*
13 PB4 PIO Parallel I/O, port B, bit 4*
14 PB5 PIO Parallel I/O, port B, bit 5*
15 PB6 PIO Parallel I/O, port B, bit 6*
16 PB7 PIO Parallel I/O, port B, bit 7*
17 PC0 PIO Parallel I/O, port C, bit 0*
18 PC1 PIO Parallel I/O, port C, bit 1*
19 PC2 PIO Parallel I/O, port C, bit 2*
20 PC3 PIO Parallel I/O, port C, bit 3*
21 RXD1 SIO COM1 serial port, RXD pin
22 TXD1 SIO COM1 serial port, TXD pin
23 CTS1 SIO COM1 serial port, CTS pin
24 RTS1 SIO COM1 serial port, RTS pin
25 DCD1 SIO COM1 serial port, DCD pin
26 DSR1 SIO COM1 serial port, DSR pin
27 DTR1 SIO COM1 serial port, DTR pin
28 RI1 SIO COM1 serial port, RI pin
29 RESIN RESET Reset input
30 TX+ LAN Ethernet interface, TX+ pin
31 TX- LAN Ethernet interface, TX- pin
32 GND ---- Ground
Table A1-1: ADNP/1520 pinout – pin 1 to 32
The PIO pins 1 to 20 are driven by an in-system programmable (ISP) high density
PLD (ispMACH256 or similar). It is possible to change the function of these pins
over the ADNP/1520 JTAG interface. Please contact our support staff for more in-
formation.