SRS Labs SR445A, Руководство пользователя

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Circuit Description
(The four amplifier channels are identical. This description uses reference designators for
the top channel.)
The input is terminated into 50
Ω by the parallel combination of R100 & R101. The input
signal is coupled via a 47 Ω resistor to the high speed “clamp-amp”, U100. U100 is
configured as a non-inverting gain of 2× amplifier. Pins 8 & 5 on U100 define input
clamping thresholds of ±0.31Vdc. If the input signal exceeds these thresholds then U100
will use the clamping thresholds as inputs thereby limiting its output to ±0.62Vdc. This
prevents the output of U100 from overdriving the next gain stage.
Input signals in excess of ±1.4Vdc are shunted to ground via the input protection diodes
D100 & D101. Normally both the diodes in D100 are reversed biased and so they do not
interfere with the signal. The diodes in D101 are forward biased by R103 & R104. When
the input signal exceeds ±1.4Vdc (7× the full scale input), one of the diodes in D100 will
turn “on” thereby limiting the input to U100 to a safe level.
The gain of U100 can be adjusted by ±10% by P100, which is calibrated at the factory to
set the overall gain of the channel to 5× when terminated into a 50
Ω load. The output of
U100 is passed to the next gain stage via R112, a 47 Ω resistor.
The next stage has a fixed gain of 5× with an adjustable offset and adjustable high
frequency response. The gain of U101 is set by R115 & R116. The offset, adjusted by
P101 and injected by R117, is nulled during calibration. The high frequency response of
U101 is affected by the source impedance of its input signal and its feedback network.
Turning P102 clockwise decreases the source impedance of the feedback signal and
increases the high frequency response of the gain stage. P102 is adjusted during
calibration for an optimum pulse response providing a typical -3dB bandwidth of
350MHz.
The output from U101 is passed to the front panel output BNC via the parallel resistors
R118 & R119, providing a 50
Ω output impedance. These resistors, in combination with
the 50 Ω load resistor (provided by the user), attenuate the signal by 2× so that the overall
gain is 5×.
Overloads are detected at the output of the second gain stage, U101. A positive overload
is rectified by D102 and charges C107. A negative overload is rectified by D102 and
discharges C106. One of the comparators in U102 will be driven low when the voltage on
C106 or C107 exceeds ±1.7V. The driven comparator discharges C108 from +5V to -5V.
C108 will be slowly recharged to +5V by R128, a 1M
Ω resistor, thereby stretching the
overload signal to about 10ms. One of the comparators in U504 (sheet 3 of the
schematics) drives the front panel overload LED until the voltage on C108 recharges
above ground. This overload detection will detect overloads as short as 3ns.