RadioProcessor-G
System Architecture
Figure 1 presents the architecture of the RadioProcessor-G, which consists of four major components: the data
acquisition core, the excitation core, the gradient control core, and the PulseBlaster timing engine, which provides high-
resolution timing control for the entire system.
The acquisition core captures an incoming RF signal using a high-speed, high resolution Analog to Digital converter
(ADC). This signal is then demodulated digitally using quadrature detection, and is then filtered to reduce the signal to
baseband. The detection and filtering system is highly configurable and can easily be customized by the user for a wide
variety of applications. The baseband signal can then be stored in an internal RAM. This data is then available to be
retrieved by the host computer at the user's convenience.
The excitation core can produce both RF Analog signals as well as digital outputs. The RF output is generated using
an internal DDS (Direct Digital Synthesis) core, and can generate frequencies from DC up to 150 MHz. The generated
signal is converted to the Analog output by an on-board digital-to-analog converter (DAC) This DDS core also drives the
detection of the acquisition core, so signal coherence is maintained between acquisition and excitation cores.
The gradient core controls three analog outputs that can be used to generate pulses with customizable durations and
varying amplitudes of both positive and negative voltages. A standard application of the RadioProcessor-G uses these
outputs to control the gradient coils for an MRI system, but they can also be used for gradient enhanced spectroscopy or
diffusion applications.
At the heart of the system is the PulseBlaster™ pulse/pattern generator timing core, which uses a robust
instruction set designed to allow the creation of complex pulse sequences with ease. This timing core controls
all aspects of the systems functionality, such as triggering data acquisition, controlling the frequency and
gating RF output, etc. This core also controls the high resolution programmable digital outputs for controlling
external hardware. Four digital outputs are available by default.
2017-09-04
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www.spincore.com
Figure 1:
RadioProcessor Model G Architecture.
The master clock oscillator signal is derived from an on-chip PLL
circuit typically using a 50 MHz on-board reference clock.
RadioProcessor-G
Master clock
ADC
DAC
PCI
Interface
Internal
RAM
Digital Quadrature
Detection
Digital Filtering
(user-customizable)
Phase and Frequency
Registers, Gating
NCO
Excitation
core
Acquisition core
PulseBlasterTM
Timing Core
Incoming Signal
Host PC
Signal
Averaging
RF Excitation
signal
Digital Output
Signals
Gradient
core
Gradient DAC controller
DAC
Analog Gradient
Control Signals
