PCI.212 Manual
31.03.2004
Page 23 of 25
Data format
Data will be read out in 2th complement. Normally the upper 4 bit (bit 12..bit 15) will be sign expanded in hardware. With this feature it
is possible to use the read data directly as signed 16 bit integer values.
If the option digital inputs is installed and the register SPC_PATTERNENABLE is set, the digital inputs will be read out in the upper four bits
of the both channels. In this case it is necessary to divide the data in the two analogue and the eight digital channels before processing the
data.
SPC_PATTERNENABLE = 0
SPC_PATTERNENABLE = 1
bit
channel 0
channel 1
channel 0
channel 1
0
AD0 0 (LSB)
AD1 0 (LSB)
AD0 0 (LSB)
AD1 0 (LSB)
1
AD0 1
AD1 1
AD0 1
AD1 1
2
AD0 2
AD1 2
AD0 2
AD1 2
3
AD0 3
AD1 3
AD0 3
AD1 3
4
AD0 4
AD1 4
AD0 4
AD1 4
5
AD0 5
AD1 5
AD0 5
AD1 5
6
AD0 6
AD1 6
AD0 6
AD1 6
7
AD0 7
AD1 7
AD0 7
AD1 7
8
AD0 8
AD1 8
AD0 8
AD1 8
9
AD0 9
AD1 9
AD0 9
AD1 9
10
AD0 10
AD1 10
AD0 10
AD1 10
11
AD0 11 (MSB)
AD1 11 (MSB)
AD0 11 (MSB)
AD1 11 (MSB)
12
AD0 11
AD1 11
Digi 0
Digi 4
13
AD0 11
AD1 11
Digi 1
Digi 5
14
AD0 11
AD1 11
Digi 2
Digi 6
15
AD0 11
AD1 11
Digi 3
Digi 7
example for dividing the channels:
LQW'DWD>/HQ@'DWD>/HQ@
LQW'LJL>/HQ@'LJL>/HQ@'LJL>/HQ@
6SF6HW3DUDP63&B3$77(51(1$%/(
6SF*HW'DWD/HQGDWDSWU'DWD
6SF*HW'DWD/HQGDWDSWU'DWD
IRUL L/HQL
^
'LJL>L@ 'DWD>L@!! [GLJLWDOFKDQQHO
'LJL>L@ 'DWD>L@!! [GLJLWDOFKDQQHO
'LJL>L@ 'DWD>L@!! [GLJLWDOFKDQQHO
'DWD>L@ 'DWD>L@!!VLJQH[WHQVLRQDQDORJXHFKDQQHO
'DWD>L@ 'DWD>L@!!VLJQH[WHQVLRQDQDORJXHFKDQQHO
`