PCI-208 / CPCI.208 manual
31.03.2004
Page 25 of 30
Features register
All of this features Registers may be set by writing a 1 or cleared by writing a 0. Some features may only be used if this features is
installed on the board (see PCI Features above).
register name
reg no.
r/w
SPC_EXTERNALCLOCK
20100
r/w the external clock will be used for recording. The external clock is allowed in the range 1
MHz to 100 MHz.
SPC_EXTERNOUT
20110
r/w enables the clock output on connector 3 of the board. Not possible if SPC_EXTERNALCLOCK
is enabled.
SPC_TRIGGEROUT
40100
r/w Enables the trigger output on connector 2 of the board. Not possible if the triggermode is set
to external TTL trigger rising or falling edge.
SPC_50OHM0
30030
r/w set the channel 0 to 50
:
input resistance (default is 1 M
:
)
SPC_50OHM1
30130
r/w set the channel 1 to 50
:
input resistance (default is 1 M
:
)
SPC_DIGITAL0
30050
r/w enable recording of digital inputs for channel 0
SPC_DIGITAL1
30150
r/w enable recording of digital inputs for channel 1
SPC_NOPRETRIGGER
200600
r/w when set to 1 the trigger sequencer is armed immediately after starting the board. The
memory is not filled with pretrigger data. This may result in the loss of pretrigger data!
SPC_RUNINTENABLE
290000
r/w enables the generation of an interrupt at the end of recording. The used interrupt line may be
read out with the register SPC_PCIINTERRUPT
Additional feature register of CPCI.208
Register name
reg no.
r/w
SPC_CLOCK50OHM
20120
r/w set the clock input to 50
:
input resistance
SPC_TRIGGER50OHM
40110
r/w set the trigger input to 50
:
input resistance
Triggermode register
Register name
reg no.
r/w
SPC_TRIGGERMODE
40000
r/w triggermode for recording.
Triggermodes
value
TM_SOFTWARE
0
recording will start immediately.
TM_CH0POS
10000
wait for rising edge on channel 0 at triggerlevel
TM_CH0NEG
10010
wait for falling edge on channel 0 at triggerlevel
TM_CH1POS
10100
wait for rising edge on channel 1 at triggerlevel
TM_CH1NEG
10110
wait for falling edge on channel 1 at triggerlevel
TM_TTLPOS
20000
wait for external TTL trigger rising edge.
TM_TTLNEG
20010
wait for external TTL trigger falling edge.
TM_GATELOW
30000
gated sampling (option) gate is TTL LOW
TM_GATEHIGH
30010
gated sampling (option) gate is TTL HIGH
Triggerlevel register
The triggerlevel is an 4 bit value which will be compared with the upper 4 bit of the ADC data.
register name
reg no.
r/w
SPC_TRIGGERLEVEL
42000
r/w triggerlevel for the triggermodes TM_CH0/1POS/NEG
triggerlevel
r
200 mV
r
500 mV
r
1 V
7
+175.0 mV
+437.5 mV
+0.875 V
6
+150.0 mV
+375.0 mV
+0.750 V
...
1
+25.0 mV
+62.5 mV
+0.125 V
0
0.0 mV
0.0 mV
0 V
-1
-25.0 mV
-62.5 mV
-0.125 V
...
-7
-175.0 mV
-437.5 mV
-0.875 V
-8
-200.0 mV
-500.0 mV
-1.000 V
stepsize
25.0 mV
62.5 mV
0.125 V
