Distributor of Spectrum Digital Inc: Excellent Integrated System Limited
Datasheet of 702570 - TARGET ADAPTER CBL 20P CTI JTAG
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Spectrum Digital, Inc
3-8
XDS560R JTAG Emulator Installation Guide
3.4.1 Emulation Timing Calculations
The following examples help you calculate emulation timings in your system. For actual
target timing parameters, see the appropriate device data sheet.
Assumptions:
t
su(TTMS)
Setup time, target TMS/TDI before TCK high
10 ns
t
pd(TTDO)
Delay time, TCK low to valid target TDO
15 ns
t
pd(bufmax)
Delay time, target buffer - maximum
10 ns
t
pd(bufmin)
Delay time, target buffer - minimum
1 ns
T(
bufskew)
Skew time, target buffer between two devices
1.35 ns
in the same package:
[ t
d(bufmax)
-
t
d(bufmin)
] x 0.15
T
(TCKfactor)
40/60 clock duty cycle
0.4(40%)
Given in Table 2 above:
t
d(TMSmax)
Delay time, emulator TMS/TDI valid
31 ns
from TCK_RET high
t
su(TDOmin)
Setup time, TDO before emulator
2.5 ns
TCK_RET high, minimum 2.5 ns
There are two key timing paths to consider in the emulation design:
❏
The TCK_RET-to-TMS/TDI path, called t
pd(TCK_RET-TMS/TDI)
, and
❏
The TCK_RET-to-TDO path, called t
pd(TCK_RET-TDO)
.
Of the following two cases (Equation 3-1 and Equation 3-2), the
worst-case
path delay
is calculated to determine the maximum system test clock
frequency.
Equation 3-1. Key Timing Path Case 1
Case 1: Single processor, direct connection, TMS/TDI timed from TCK_RET high.
t
pd(TCK_RET - TMS/TDI)
= t
pd(TMSmax)
+ t
su(TTMS)
= 31 ns + 10 ns
= 41 ns (24.4 MHz)
t
pd(TCK_RET - TDO)
= [ t
d(TTDO)
+ t
su(TDOmin)
] / t
(TCKfactor)
= [15 ns + 2.5 ns] / 0.4
= 43.75 ns (22.9 MHz)
In this case, the TCK_RET-to-TDO path is the limiting factor.
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