Option Gated Replay
Output modes
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Option Gated Replay
The option Gated Replay allows the data generation controlled by an external gate signal. Data will only be output, if the programmed gate
condition is true.
Output modes
Standard Mode
Data will be replayed as long as the gate signal fulfills the gate
condition that has had to be programmed before. At the end of
the gate interval the replay will be stopped and the board will
pause until another gates condition is detected. If the total
amount of data to replay has been reached the board stops im-
mediately (see figure). The total amount of samples to be re-
played can be defined by the memsize register.
The table below shows the register for enabling Gated Replay.
For detailed information on how to setup and start the standard
generation mode please refer to the relevant chapter earlier in
this manual.
FIFO Mode
The Gated Replay in FIFO Mode is similar to the Gated Replay
in Standard Mode. In contrast to the Standard mode you cannot
program a certain total amount of samples to be replayed. The
generation is running until the user stops it. The data is transfered
to the board FIFO block by FIFO block by the driver. These
blocks can be online generated by the user program.
The advantage of Gated Replay in FIFO mode is that you can
stream data online from the host system to the board, so you can
replay a huge amount of data from the hard disk with a lower
average data rate than in conventional FIFO mode. The table be-
low shows the dedicated register for enabling Gated Replay. For
detailed information how to setup and start the board in FIFO mode please refer to the according chapter earlier in this manual.
Trigger modes
General information and trigger delay
Not all of the board’s trigger modes can be used in combi-
nation with Gated Replay. All possible trigger modes are
listed below. Depending on the different trigger modes, the
chosen sample rate, the used channels and activated board
synchronization (see according chapter for details about
synchronizing multiple boards) there are different delay
times between the trigger event and the first replayed sam-
ple(see figure). This start delay is necessary as the board is
equipped with dynamic RAM, which needs refresh cycles to
keep the data in memory when the board is not replaying.
It is fix for a certain board setup.
All possible start delays in samples between the trigger
event and the first replayed sample are listed in the table
below.
Register
Value
Direction
Description
SPC_GATE
220400
r/w
Enables Gated Replay mode.
SPC_MEMSIZE
10000
r/w
Defines the total amount of samples to replay.
Register
Value
Direction
Description
SPC_GATE
220400
r/w
Enables Gated Replay mode.
