Wireless Module
2. PCB Layout Guide
2.1. PCI-e Layout Guide
1.
The PCI-e differential pair signals impedance target is 100
±
20% ohms
impedance.
2. Do not place probe or test points on any high-speed differential signal.
3. Do not route high-speed traces under or near crystals, oscillators, clock signal
generators, switching power regulators, mounting holes, magnetic devices, or ICs
that use or duplicate clock signals.
4. The traces routing don't be 90° angle.
5. For PCI-e add-in card, any layer under edge finger area should be removed.
Including ground and power layers.
6. Ensure that high-speed differential signals are routed at least 1.5 W (calculated
trace-width × 1.5) away from voids in the reference plane. This rule does not apply
where SMD pads on high-speed differential signals are voided.
7. Maximize differential pair-to-pair spacing when possible.
2.2 USB Layout Guide
1. DP/DM traces should always be matched lengths and must be no more than 4
inches in length; otherwise, the eye opening may be degraded.
2. Route DP/DM traces close together for noise rejection on differential signals, parallel
to each other and within two mils in length of each other (start the measurement at
the chip package boundary, not to the balls or pins).
3. A high-speed USB connection is made through a shielded, twisted pair cable with a
differential characteristic impedance of 90
Ω ±15%.
In layout, the impedance of DP
and DM should each be 45
Ω ± 10%.
4. DP/DM traces should not have any extra components to maintain signal integrity. For
example, traces cannot be routed to two USB connectors.
5. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and
increases the chance of picking up interference from the other layers of the board.
Be careful when designing test points on twisted pair lines; through-hole pins are not
recommended.
