Sony WRT-800A, Руководство по обслуживанию

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WRT-800A (AU)
IC
GND LX
5 4
1 2 3
4
3
1
2
LX
EXT
CE
OUT
GND
5
LX
EXT
CE
OUT
; SWITCHING TERMINAL (OPEN DRAIN)
; EXTERNAL TRANSISTOR DRIVE (CMOS OUTPUT)
; CHIP ENABLE
; STEP-UP OUTPUT VOLTAGE MONITOR
V
LX
LIMITER SLOW START V REF.
BUFFER
PWM CONTROLE
OSC
CHIP ENABLE
PHASE
COMPARATOR
–
+
2
OUT
ERROR AMP.
LX
4
GND
5
EXT
3
CE
1
–TOP VIEW–
C-MOS PWM STEP-UP DC/DC CONVERTER
OUT CE EXT
LxSW
1
2
3
4
8
7
6
5 V
EE
V
CC
_ +
_ +
DUAL OPERATIONAL AMPLIFIERS
(DUAL-SUPPLY TYPE)
–TOP VIEW–
TYPE V
CC
+ 2 to + 16V
+ 2 to + 18V
+
3 to
+
20V
+ 5 to + 12V
+ 5 to + 22.5V
+ 1 to + 3.5V
+ 2 to + 20V
+ 5 to + 16V
062/072/082/4556A/
M5218/BA15218/
33178/34182 TYPES
4580 TYPE
5532 TYPE
CXA1297 TYPE
M5219/M5220 TYPES
NJM2100 TYPE
OP-297 TYPE
OTHERS
V
EE
_ 2 to _ 16V
_ 2 to _ 18V
_
3 to
_
20V
_ 5 to _ 12V
_ 5 to _ 22.5V
_ 1 to _ 3.5V
_ 2 to _ 20V
_ 5 to _ 16V
GCELL IN
RECT IN
EXP CAP
EXP OUT
V REF
PWRON1
MUTE
IREF
GND
1
2
3
4
5
8
6
7
10K
GAINCELL
RECTIFIER
EXPADOR
IREF VCC
GND
PWRON
MUTE
VREF
BANDGAP
10K
5K
10K
M
G
30K 30K 10K
M
10K 8.6K
COMPRESSOR
RECTIFIOER
G
GAINCELL
10K
16
15
14
13
12
11
10
9
VCC
COMP CAP2
COMP IN
COMP CAP1
RECT IN
GCELL IN
COMP OUT
SUM IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GCELL IN
RECT IN
EXP CAP
EXP OUT
VREF
IREF
PWRON/
MUTE
GND
VCC
+8V
COMP CAP2
COMP IN
COMP CAP1
RECT IN
GCELL IN
COMP OUT
SUM IN
LOW POWER COMPANDOR
-TOP VIEW-
20
19
18
17
φ
R
φ
P
TEST
PLL FREQUENCY SYNTHESIZER (1.1 GHz BAND)
-TOP VIEW-
16
15
14
13
Do2
FC
LAT
DATA
PS
CK
1
2
3
4
5
6
7
8
9
10
12
11
OSCI
OSCO
Vp
Do1
LD
FIN
PHASE
COMPARATOR
PROGRAMMABLE
COUNTER
PULSE SWALLOW
PROGRAMMABLE
COUNTER
CHARGE
PUMP 1
CHARGE
PUMP 2
SHIFT RESISTOR
LATCH
φ
R
φ
P
TEST
Do2
LAT
FC
PS
DATA
CK
OSCI
OSCO
Vp
Do1
LD
FIN
1
3
4
6
10
8
15
12
13
11
17
16
20
18
14
: REFERENCE FREQUENCY INPUT
: REFERENCE FREQUENCY OUTPUT
: POWER SUPPLY FOR CHARGE PUMP,
PHASE COMPARATOR
: CHARGE PUMP 1 OUTPUT
: CHARGE PUMP 2 OUTPUT
: LOCK DETECTION SIGNAL OUTPUT
: PHASE COMPARATOR OUTPUT
: PHASE COMPARATOR OUTPUT
: CLOCK INPUT
: DATA INPUT
: LATCH INPUT
: POWER SAVE INPUT("L":POWER SAVE
MODE)
: SELECTION TERMINAL FOR PHASE OF
PHASE COMPARATOR OUTPUT AND
COUNTER OUTPUT SIGNAL TO TEST
TERMINAL
: OUTPUT FOR DIVIDING SIGNAL OF
COUNTER
OSCI
OSCO
Vp
Do1
Do2
LD
φ
P
φ
R
CK
DATA
LAT
PS
FC
TEST
NC NC
NC
GND
Vcc
(+3V)
8
7
6
5
1
2
3
4
IN
IN
IN
OUT
CS
SK
DI
DO
VDD
NC
ORG
GND
(+5V)
1
2
3
CS
DI
6
ORG
4
DO
VCC GND
MEMOROY ARRAY
R8 · 8
OR
64 · 16
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
ORG
DI
CS
SK
3
1
2
6
ADDRESS
DECODER
OUTPUT
BUFFER
4
DO
INPUT
CS
DI
SK
ORG
OUTPUT
DO
; CHIP SELECT
; DATA INPUT
; SERIAL CLOCK
; ORGANIZATION
; DATA OUTPUT
C-MOS 1024 (64
·
16 or 128
·
8) BIT
SERIAL ELECTRICALLY ERASABLE PROM
-TOP VIEW-
AT93C46-10SI-2.7-E2 (ATMEL)FLAT PACKAGE
CXA1786N-T4 (SONY)FLAT PACKAGE
NE578D-T (SIGNETICS)FLAT PACKAGE
NJM2100E (JRC)FLAT PACKAGE
NJM2100E-T1
RH5RH303B-T1 (RICOH)
5-2