Sony VPL-HS50, Руководство по обслуживанию

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6-24
VPL-HS50/HS51
6-24
C C
C (10/19) K4D263238F-UC50T (IC1102)
54 55
CKE
53 28 27 26 25
DMI
56
TIMING REGISTER
PROGRAMMING REGISTER
LATENCY & BURST LENGTH
COLUMN DECODER
64
64
32
32
x 32
1M x 32
1M
x
32
1M x 32
1M
x
32
DATA INPUT REGISTER
SERIAL TO PARALLEL
BANK SELECT
CK, CK
CK, CK
CK, CK
CK, CK
ADDR
LWE
LDMI
LRAS
LCKE
LCAS LWCBR
LDMI
LCBR LWE
LRAS LCBR
CS
RAS CAS
WE
.
COL.
B
UFFER
R
O
W DECODER
SENSE AMP
2-BIT PREFETCH
OUTPUT B
UFFER
STR
OBE
GEN.
INPUT BUFFER
I/O CONTR
OL
REFRESH COUNTER
R
O
W B
UFFER
ADDRESS REGISTER
DLL
94 DQS
1 3 4 6 7
9 10 12 13
17 18 20 21
60 61 63 64
68 69 71 72
74 75 77 78
80 81 83 84
. . . .
. . .
. . .
. . .
. . .
. . .
. . .
C (10/19) NE57814DD.118 (IC1101)
5
VDD
4
VD
VSS
100k Z
100k
Z
EXTREFIN
VTT
REFOUT
VTT SENSE
7
8
3
1
STANDBY
OVERTEMP
CONTROL
POWER
MANAGER
OVERCURRENT
CONTROL
6
2
C (12/19) ICS342M-05LF (IC1303)
OTP ROM
WITH PLL
DIVIDER
VALUES
CRYSTAL
OSCILLATOR
PLL CLOCK
SYNTHESIS ,
SPREAD SPECTRUM AND
CONTROL CIRCUITRY
6
2
3 7
VDD
GND RDTS
4 CLK1
5 CLK2
1 X1/CLK
8
X2
SEL
C (12/19) MX29LV800BTTC-70G-89PW (IC1305)
PROGRAM/ERASE
HIGH VOLTAGE
CONTROL
INPUT
LOGIC
ADDRESS
LATCH
AND
BUFFER
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS
GATE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
SENSE
AMPLIFIER
PROGRAM
DATA LATCH
I/O BUFFER
PGM
DATA
HV
MX29LV800T/B,
MX29LV800AT/AB
X-DECODER
Y-
DECODER
26 CE
28 OE
11
WE
12 RESET
1
8
.
A0-A11 16
.
48
25
29
36
.
Q0-Q15/A-1 38
45