Sony Vaio PCGA-CRWD1, Руководство по обслуживанию

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4-5
IC
Confidential
PCGA-CRWD1 (AM)
Pin Function
Signal Name PIN I/O Reset Description
1394Phy Interface (LVDD)
1 D7 98 B Hi-Z (MSB)
2 D6 99 B Hi-Z
3 D5 100 B Hi-Z
4 D4 101 B Hi-Z Phy Data Bus
5 D3 102 B Hi-Z
6 D2 104 B Hi-Z
7 D1 105 B Hi-Z
8 D0 106 B Hi-Z (LSB)
9 CTL1 107 B Hi-Z
10 CTL0 108 B Hi-Z
11 LREQ 115 O Lo Link Request Signal to Phy
12 LPS 96 O Lo Link Power Status Signal to Phy
13 LINKON 95 I - Link ON Signal from Phy
14 XISO 110 I - Select Option Phy(L : Annex-J Isolation)
15 BHEN 109 I - Bus Holder Enable Signal (H : Enable)
16 CNA 111 I Cabele Not Active
17 PD 97 O Power Down Enable
18 SCLK 113 I - Clock Signal (49.576MHz) from Phy
Signal Name PIN I/O Reset Description
IDE Interface (HVDD)
19 HDD15 72 B Hi-Z (MSB)
20 HDD14 74 B Hi-Z
21 HDD13 77 B Hi-Z
22 HDD12 79 B Hi-Z
23 HDD11 81 B Hi-Z
24 HDD10 84 B Hi-Z
25 HDD9 86 B Hi-Z
26 HDD8 88 B Hi-Z IDE Data Bus
27 HDD7 89 B Hi-Z
28 HDD6 87 B Hi-Z
29 HDD5 85 B Hi-Z
30 HDD4 82 B Hi-Z
31 HDD3 80 B Hi-Z
32 HDD2 78 B Hi-Z
33 HDD1 76 B Hi-Z
34 HDD0 73 B Hi-Z (LSB)
35 HDMARQ 71 B Hi-Z IDE Request Signal
36 XHIOW 70 B Hi-Z IDE Writw Signal
37 XHIOR 69 B Hi-Z IDE Read Signal
38 HIORDY 68 I - IDE IO Rdy Signal
39 XHDMACK 66 B Hi-Z IDE DMA Acknowledge Signal
40 HINTRQ 65 I - IDE Interrupt Signal
41 XHPDIAG 63 I - IDE PDIAG Signal
The control signal with which "X" was attached to the head of a signal name is low active. (X2SPD
is removed.)
Signal Name PIN I/O Reset Description
IDE Interface (HVDD)
42 HDA2 61 Otr Hi-Z (MSB)
43 HDA1 64 Otr Hi-Z IDE Address Signal
44 HDA0 62 Otr Hi-Z (LSB)
45 XHCS1 59 Otr Hi-Z IDE Chip Select Signal
46 XHCS0 60 Otr Hi-Z IDE Chip Select Signal
47 XHDASP 56 I
—
IDE DASP Signal
48 XHRST 90 Otr Hi-Z IDE Reset Signal
Signal Name PIN I/O Reset Description
C33 External Interface (HVDD)
49 AD23 54 O Lo (MSB)
50 AD22 53 O Lo
51 AD21 52 O Lo
52 AD20 51 O Lo
53 AD19 50 O Lo
54 AD18 49 O Lo
55 AD17 44 O Lo
56 AD16 43 O Lo
57 AD15 42 O Lo CPU Address Bus
58 AD14 41 O Lo
59 AD13 40 O Lo
60 AD12 39 O Lo
61 AD11 38 O Lo
62 AD10 36 O Lo
63 AD9 35 O Lo
64 AD8 34 O Lo
65 AD7 33 O Lo
66 AD6 32 O Lo
67 AD5 31 O Lo
68 AD4 30 O Lo
69 AD3 28 O Lo
70 AD2 27 O Lo
71 AD1 26 O Lo
72 AD0 25 O Lo (LSB)
73 DT15 20 B Hi-Z (MSB)
74 DT14 19 B Hi-Z
75 DT13 18 B Hi-Z
76 DT12 17 B Hi-Z
77 DT11 16 B Hi-Z
78 DT10 15 B Hi-Z
79 DT9 14 B Hi-Z
80 DT8 12 B Hi-Z CPU Data Bus
81 DT7 11 B Hi-Z
82 DT6 10 B Hi-Z
83 DT5 9 B Hi-Z
84 DT4 8 B Hi-Z
85 DT3 7 B Hi-Z
86 DT2 6 B Hi-Z
87 DT1 4 B Hi-Z
88 DT0 3 B Hi-Z (LSB)
Signal Name PIN I/O Reset Description
C33 External Interface (HVDD)
89 P07 154 B I/O Port 07
90 P06 153 B I/O Port 06
91 P05 152 B I/O Port 05
92 P04 151 B I/O Port 04
93 SRDY(P03) 150 B Serial I/O Rdy Signal Input / I/O Port 03
94 SCLK(P02) 149 B Serial I/O Rdy Signal Input / I/O Port 02
95 SOUT(P01) 147 B Serial I/O Rdy Signal Input / I/O Port 01
96 SIN(P00) 146 B Serial I/O Rdy Signal Input / I/O Port 00
97 K67 144 I
98 K66 143 I
99 P23 142 B
100 P22 141 B
101 P21 136 B
102 P20 135 B
103 XCE10_EX 134 O Hi External Memory Area 10 Chip Enable
104 XCE9 133 O Hi Area 9 Chip Enable
105 XCE6 131 O Hi Area 6 Chip Enable
106 EA10M2 164 I Area 10 Boot Mode Select 2
107 EA10M1 163 I Area 10 Boot Mode Select 1
108 EA10M0 162 I Area 10 Boot Mode Select 0
109 XWAIT 145 I Wait Cycle Input
110 XRD 24 O Hi Read Signal
111 XWRH 22 O Hi High Byte Write Signal
112 XWRL 23 O Hi Low Byte Write Signal
113 BCLK 182 O Hi Bus Clock Signal
C33 External Interface (LVDD)
114 P14 166 B Lo I/O Port 14 (ICD)
115 P13 167 B Lo I/O Port 13 (ICD)
116 P12 168 B Lo I/O Port 12 (ICD)
117 P11 169 B Lo I/O Port 11 (ICD)
118 P10 174 B Lo I/O Port 10 (ICD)
119 DSIO 175 B Debug Serial I/O : Use communication with ICD33.
Signal Name PIN I/O Reset Description
Clock Generator Terminal
120 OSC4 172 O High Speed Ocillation Output
121 OSC3 171 I
High Speed Ocillation Input (XTAL/Ceramic Oscillation or
External Clock Input)
122 PLLS1 161 I PLL Setting 1
123 PLLS0 160 I PLL Setting 0
124 PLLC 158 — PLL Capacitor Connection Terminal
Signal Name PIN I/O Reset Description
Other Terminal
125 ICEMD 179 I High Impedance : All outputs are set to Hi.
126 X2PSDX 155 I
Double Speed Mode Setup (H : CPU Clock = BCLK X 1 L
: CPU Clock = BCLK X 2)
127 XNMI 177 I NMI Input
128 XRESET 178 I Initial Reset
129 HCLK 181 O 1/2 Divide Output of SCLK
130 TVEP 58 - Flash Test
Signal Name PIN I/O Reset Description
Test Terminal
131 TI8 121 I
132 TO7 122 O - (MSB)
133 TO6 123 O -
134 TO5 124 O -
135 TO4 125 O -
136 TO3 126 O -
137 TO2 127 O -
138 TO1 128 O -
139 TO0 129 O - (LSB)
140 FLSTST 55 I - Flash Test
141 RAMTST 56 I - SRAM Test
142 MonxWait 132 O - XWAIT Monitor
143 MonxInt 120 O - XINT Monitor
Power Supply Terminal
HVDD - P H Power Supply (5V) 5,21,37,67,83,130,165,176(Eight)
LVDD - P L Power Supply (3.3V) 1,47,93,103,114,139,(Six)
VSS - P
GND
148,157,159,170,173,180,184,13,29,46,57,75,92,112,116,
117,118,119,138(Nineteen)
N.C. Terminal
N.C. - - 2,45,48,91,94,137,140,183(Eight)
TC7S14FU (TE85R) (TOSHIBA)
SCHMITT INVERTER
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