1
2
3
4
5
6
7
8
9
10
11
14
15
12
13
A
B
C
D
E
F
G
H
I
J
37
37
STR-DH700
STR-DH700
5-20. SCHEMATIC DIAGRAM — HDMI RE BOARD (2/2) — • Refer to page 17 for Circuit Boards Location.
MCK
3.3
0
0
3.3
3.3
3.3
7.3
5.0
3.2
3.2
3.6
3.6
0
0
1.8
1.8
5
5
3.3
3.3
3.3
3.3
HDMI BOARD (2/2)
TK11150CSCL-G
IC3516
0.01
C3579
0.22
C3584
1
C3585
0.1
C3558
0.1
C3562
0.1
C3564
0.1
C3570
0.1
C3569
0.1
C3568
0.1
C3567
0.1
C3566
C3561 0.1
C3563 0.1
C3557 0.1
0.1
C3555
0.1
C3556
10k
R3581
470
R3580
47 6.3V
C3573
1006.3V
C3572
6.3V
47
C3571
4V
220
C3574
4.7k
R3583
4.7k
R3584
R3576 47
10k
R3579
R3597
0
100
R3570
R3593
10k
1.8k
R3599
1.8k
R3600
0.1
*C3591
R3585
0
R3586
0
R3587
0
R3588
0
R3589
0
R3590
0
R3591
0
R3592
0
R3577 47
1
2
3
4
5
5P
CN3509
+4V
+4V
DGND
DGND
+6V
D1
G2
S2
D2
G1
S1
SSM6N15FU(TE85R)
Q3504
DATA BUFFER
9 10 11 12 13 14 15 16 17 18 19 20
10k
R3634
0.33
*C3590
0uH
FB3505
0uH
FB3504
0uH
FB3512
0uH
FB3513
0uH
FB3514
0.1
C3630
0.1
C3631
0.1
C3632
R3578 100
R3660 0
6.3V
220
C3575
16V
100
C3586
6.3V
100
*C3580
6.3V
100
*C3576
10V
47
*C3593
R3676
100
47
R3582
16V
100
*C3621
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CN3511
CEC
H_RESET
MAINCPU_UART_RX
MAINCPU_UART_TX
REG_CTL
MUTE
SPDIF
SD0
SD1
SD2
SD3
LRCK
BCK
GND
MCK
GND
GND
FB3515
0uH
6.3V
C3646
100
*R3806
0
6.3V
100
C3655
0.1
C3656
R3830 0
R3837 220
R3838 150
FB3517 0uH
FB3516 0uH
0.1
C3657
*C3658 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
19P
CN3504
47k
R3642
1SR154-400TE-25
D3510
10k
R3843
1SS367-T3SONY
D3502
1SS367-T3SONY
D3501
TX_RST
R3832 0
R3835 220
R3834 220
R3833 220
R3831 220
E
ET3503
R3847 0
R3836 0
1k
R3848
1.5k
*R3857
22k
*R3858
10k
*R3859
3.3k
*R3860 4.7k
*R3861
GND
1
*C3661
1
*C3662
10k
*R3862
BCK,LRCK,MCK,SD[0-3],SPDIF
SPDIF
MCK
SD[3]
SD[2]
SD[1]
BCK
LRCK
SD[0]
CSCL
CSDA
Q[23]
Q[22]
Q[21]
Q[20]
Q[19]
Q[18]
Q[17]
Q[16]
Q[15]
Q[14]
Q[13]
Q[12]
Q[11]
Q[10]
Q[9]
ODCK
Q[8]
Q[7]
Q[6]
Q[5]
Q[4]
Q[3]
Q[2]
Q[1]
Q[0]
DE
HSYNC
VSYNC
BCK
LRCK
SD[3]
SD[2]
SD[1]
SD[0]
CGND
DATA 2 -
DATA 2 +
DATA 1 SHIELD
DATA 1 +
RESERVE(N.c)
DATA 0 SHIELD
DATA 1 -
+5V POWER
CLOCK SHIELD
DATA 0 -
DATA 2 SHIELD
CLOCK -
CEC
DDC/CEC GND
HOT PLUG DET
SCL(5V)
SDA(5V)
CLOCK +
DATA 0 +
HDMI OUT
Schottky Diode.
Schottky Diode.
At bottom Right side
XX
HPD Detection
IC3533
0.01
C3619
10k
R3796
R3798
0
R3867 1M
10k
R3700
10k
R3601
10k
R3602
10k
R3603
R3604 10k
10k
R3605
47
R3608
47
R3609
47
R3610
47
R361
1
47
R3612
47
R3614
47
R3615
47
R3616
47
R3622
47
R3621
R3624 22
R3625 22
6.3V
47
C3625
R3633
0
0uH
FB3506
0.1
C3620
0.1
C3615
0.1
C3616
0.1
C3617
0.1
C3618
X3502
10MHz
10k
R3797
100
R3645
1.8k
R3652
1.8k
R3653
R3790
10K
47
R3799
47
R3623
47
R3613
10k
*R3791
*R3793
10k
1
2
3
4
5
6
7
CN3510
7P
CNVSS
RESET
232C_OUT(VU_TX)
GND
232C_IN(VU_RX)
GND
3.3V
47
R3813
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TX_RST
RX_RST
RX_HPD[1]
RX_INT
TMDS_S[2]
TMDS_S[3]
TMDS_OEB
P5V_SELA
EEPROMSEL[1]
CSCL
CSDA
P5V_SELB
TMDS_S[1]
SPDIF_SW is for Selection of SPDIF signal between Audio Return
17P
A1
A3
A5
A7
A2
A4
A6
A8
*C3659 1
SPDIF
OUT
FLASH
PROGRAMMING
3.3
3.3
3.3
3.3
0
0
0
0
1.8
0
0
0
0
0
0
0
0
0
0
3.3
1.8
1.8
3.3
0.5
1.3
3.3
1.8
3.3
0.9
3.3
0
2.9
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
0
0
0
0
0
0
0
0
1.8
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.8
3.3
3.3
3.3
0
0
0
3.3
3.3
0
0
0
0
0
0
0
0
0
0
3.3
1.8
0
0
0
0
0
0
3.3
3.3
3.3
3.3
3.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.3
3.3
3.3