Sony STR-DA4400ES, Руководство по обслуживанию

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STR-DA4400ES
131
• IC Pin Function Description
DSP BOARD IC5002 ADSST-AVR-1132 (DSP1)
Pin No. Pin Name I/O Description
A1 CLKCFG0 I Clock frequency setting terminal
A2 XTAL O System clock output terminal (12.288 MHz)
A3 TMS - Not used
A4 TCK - Not used
A5 TDI - Not used
A6 CLKOUT - Not used
A7 TDO - Not used
A8 EMU - Not used
A9 MOSI I Serial data input from the DSP controller
A10 MISO O Serial data output to the DSP controller
A11 SPIDS I Serial data latch pulse signal input from the DSP controller
A12 VDDINT - Power supply terminal (+1.2V)
A13, A14 GND - Ground terminal
B1 CLKCFG1 I Clock frequency setting terminal
B2 GND - Ground terminal
B3 VDDEXT - Power supply terminal (+3.3V)
B4 CLKIN I System clock input terminal (12.288 MHz)
B5 TRST - Not used
B6 AVSS - Ground terminal
B7 AVDD - Power supply terminal (+1.2V)
B8 VDDEXT - Power supply terminal (+3.3V)
B9 SPICLK I Serial data transfer clock signal input from the DSP controller
B10 RESET I Reset signal input from the DSP controller "L": reset
B11 VDDINT - Power supply terminal (+1.2V)
B12 to B14 GND - Ground terminal
C1, C2
BOOTCFG1,
BOOTCFG0
I Boot mode setting signal input from the DSP controller
C3, C12,
C13
GND - Ground terminal
C14, D1 VDDINT - Power supply terminal (+1.2V)
D2, D4 to
D6, D9 to
D11, D13
GND - Ground terminal
D14, E1 VDDINT - Power supply terminal (+1.2V)
E2, E4 to
E6, E9 to
E11, E13
GND - Ground terminal
E14 P_ERROR O PLL lock error signal and data error fl ag output to the DSP2 and DSP controller
F1 FLAG1 I
Audio muting control signal input from the digital audio interface receiver, video system
controller or HDMI receiver
F2 FLAG0 O Interrupt request signal output to the DSP controller
F4 to F6,
F9 to F11
GND - Ground terminal
F13 NONAUDIO I PCM audio data input from the digital audio interface receiver or video system controller
F14 DPFSCK I
Master clock signal input from the digital audio interface receiver, digital audio processor,
HDMI receiver or XM receiver
G1 AD7 I/O
Two-way data bus with S-RAM and fl ash memory and address signal output to the address
latch
G2 VDDINT - Power supply terminal (+1.2V)
G13 VDDEXT - Power supply terminal (+3.3V)
G14 DPBCK I
Bit clock signal input for PCM audio input from the digital audio interface receiver, digital
audio processor, HDMI receiver or XM receiver
H1 AD6 I/O
Two-way data bus with S-RAM and fl ash memory and address signal output to the address
latch
H2 VDDEXT - Power supply terminal (+3.3V)
H13 DPLRCK I
L/R sampling clock signal input for PCM audio input from the digital audio interface receiver,
digital audio processor, HDMI receiver or XM receiver
H14 DPDVBCK O Bit clock signal output for PCM audio output to the DSP2