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Pin No.
Pin Name
I/O
Function
56
IBIAS
I
Analog bias input terminal
57
AGND
—
Analog ground terminal
58
BATTERY
I
Battery voltage detection input terminal
59
AFC
O
Not used (open)
60
AGC
O
Auto gain control signal output to the RF unit
61
CALLER-ID
O
Not used (open)
62
PARKP
I
Charge detection input terminal “L”: charge on
63
VDDC
—
Power supply terminal (+5V) (for core)
64
VSSP
—
Ground terminal (for pad)
65
SYNDATA
O
Synthesizer data output to the RF unit
66
SYNTH5MCLK
O
Synthesizer reference oscillator output to the RF unit (9.62 MHz)
67
LCDRS
O
Register selection signal output to the liquid crystal display unit (LCD501)
“L”: instruction register, “H”: data register
68
LED4
O
LED drive signal output terminal “L”: LED on Not used (open)
69
JOG (A)
I
Jog dial pulse input of the rotary encoder (SW601) (A phase input)
70
JOG (B)
I
Jog dial pulse input of the rotary encoder (SW601) (B phase input)
71
SYNCLK
O
Synthesizer clock signal output to the RF unit
72
SYNSTB
O
Synthesizer strobe signal output to the RF unit
73
VDDP
—
Power supply terminal (+5V) (for pad)
74
VSSP
—
Ground terminal (for pad)
75
SYNEN
O
Synthesizer power control signal output to the RF unit “H”: enable
76
NVDI
I/O
Two-way data bus with the EEPROM (IC502)
77
NVDO
O
Clock signal output to the EEPROM (IC502)
78
LCDRW
O
Data read/write selection signal output to the liquid crystal display unit (LCD501)
“L”: data write, “H”: data read
79
TXEN
O
TX system enable signal output to the RF unit “H”: enable
80
TXPWR1
O
PA power selection signal output to the RF unit
81
GPIOB6
O
Not used (open)
82
TXRXSEL
O
TX/RX selection signal output to the RF unit “L”: RX, “H”: TX
83
RINGOFF
I
RING on/off switch (S501) input terminal “L”: ringer off, “H”: ringer on
84
BASEP
I
Setting terminal for the base/handset selection
“L”: base unit, “H”: handset unit (CMOS receiver with pull-up)
85
TXPWR0
O
PA power selection signal output to the RF unit
86, 87
GPIOB5, GPIOB0
O
Not used (open)
88
GPIOA7
O
Muting control signal output for the speaker amplifier “H” active Not used (open)
89
LED1
O
LED drive signal output terminal “L”: LED on Not used (open)
90
VDDC
—
Power supply terminal (+5V) (for core)
91
VSSC
—
Ground terminal (for core)
92
LCDPWRP
O
Power on/off control signal output for the liquid crystal display unit (LCD501)
“L”: power on, “H”: power off
93
SLEEP
O
Not used (open)
94
GPIOB4
O
Not used (open)
95
NVCLK
O
Not used (open)
96
RESETI
I
System reset signal input from the reset signal generator (IC301) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
97
XTALI
I
Main system clock input terminal (9.6 MHz)
98
XTALO
O
Main system clock output terminal (9.6 MHz)
99
VDDP
—
Power supply terminal (+5V) (for pad)
100
VSSP
—
Ground terminal (for pad)
Содержание SPP-SS964
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Страница 30: ...SPP SS964 37 38 7 7 SCHEMATIC DIAGRAM BASE MAIN Section 2 3 See page 47 for IC Block Diagrams Page 36 Page 39 ...