Sony SPP-Q123, Руководство по обслуживанию

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SPP-Q123
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1 TEST CH O Test mode channel control. L : ACT
2 KEY LED O Key LED ON/OFF control. L : ON
3 SIG-IN I RSSI, PLL-Lock signal input terminal.
4 PLL-STB O Strobe signal output to PLL.
5 PLL-DATA O Serial data output to PLL.
6 NC – Not uaed (Open).
7 PLL-CLK O Serial clock output to PLL.
8 RX-DATA I RX data input terminal.
9 TX-DATA O TX data output terminal.
10 TX-DATA O TX data output terminal.
11 BEEP O Beep signal output.
12 HOLD I Hold control input. L : Hold
13 TX +B CTRL O TX B+ ON/OFF control. L : TX ON
14 RX +B CTRL O RX B+ ON/OFF control. (not used:Open).
15 TEST I Test terminal (connect to ground).
16 VSS – Ground.
17 OSC1 I Internal osillator (4.048MHz).
18 NC – Not used (Open).
19 NC – Not used (Open).
20 OSC2 O External osillator (4.048MHz).
21 RESET I System reset terminal. L : Reset
22 ACT3 O Intermittent reception activation control. L : ACT
23 ACT4 O Intermittent reception activation control. L : ACT
24 COL0 I Key input terminal.
25 COL1 I Key input terminal.
26 COL2 I Key input terminal.
27 COL3 I Key input terminal.
28 MIC O MIC bias output control.
29 ROW1 O Key scan output.
30 NC – Not used (Open).
31 ROW2 O Key scan output.
32 ROW3 O Key scan output.
33 ROW4 O Key scan output.
34 ROW5 O Key scan output.
35 – Not used (Open).
36 – Not used (Open).
37 BATT-LOW I Battery level signal input.
38 CHG-DET I Charge DET input terminal. H : DET
39 VDD I Power supply (+3V).
40 TEST SW I Test mode activation input. H : Start
41 – Not used (connect to ground).
42 NC – Not used (Open).
43 NC – Not used (Open).
44 TEST ACT I During test mode,causes start of intermittent operation with external input.
45 RSSI H/L O RSSI sense H/L selector. L : Low sense
46 H • MUTE O Half mute control. L : Mute ON
47 BATT-DET I Battery detection input. H : DET
48 LED O Talk LED control. L : LED ON
Pin No. Pin Name I/O Function
Pin No. Pin Name I/O Function
5-6. IC PIN FUNCTION DESCRIPTION
• IC501 SB662106A (BASE UNIT CPU)
1 STB O Strobe signal output to PLL.
2 DATA O Serial data output to PLL.
3 CLK O Serial clock output to PLL.
4 RX-DATA I RX data input terminal.
5 SIG-IN I RSSI,PLL-Lock signal input terminal.
6 H-MUTE O Half mute control output. L : Mute ON
7 TX-DATA O TX data,external system alarm output terminal.
8 VSS – Ground
9 OSC2 O External oscillator (4.048MHz).
10 OSC1 I Internal oscillator (4.048MHz).
11 VDD – Power supply terminal (+3V).
12 RESET I System reset terminal. L : Reset
13 TEST I Test terminal(connect to ground).
14 POW-DET I Power failure DET terminal. L : Power failure
15 MBR I Make 30/40 (%) selection input. H : 30%, L : 40%
16 PAGE I Page key input. H : input
17 DIAL MODE I Dial mode selection input terminal.
18 CHG-DET I Charge DET. L : Charge
19 RSSI O RSSI sensitivity selection output.
20 DP O Dial pulse ON/OFF control.
21 DTMF O DTMF output terminal.
22 TX +B CTRL I TX B+ ON/OFF control. L : TX ON
23 M1 I Channel setting for test mode.
24 M2 I Channel setting for test mode.
25 M3 I Channel setting for test mode.
26 M4 I Channel setting for test mode.
27 TEST SET1 I Test mode setting 1.
28 TEST SET2 I Test mode setting 2.
29 TEST SET3 I Test mode setting 3.
30 RING I Ring DET input. L : Ring in
• IC501 SH66358C-4H77 (HANDSET CPU)