Sony SMP-N100, Руководство по обслуживанию

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3-5. POWER BLOCK DIAGRAM
SMP-N100
3-5E
UNSW12V
DCDC6V
3.8
V
1ch
DCDC
MT
85
30
DD
R2_
1.8
V
DD
R2
_VT
T0.
9V
3.3
V
DD
R2_
1.8
V
CO
RE_
STB
3.3
V
CO
RE_
1.1
V
DD
R2
×
4
REG
1.8
V
0.9
V
効
率
90
%
REG
1.2
V
CP
U_3
.3V
A
1ch DCDC
1ch DCDC
VTT REG
1.1
V
CP
U_1
.2V
A
12
V
3.8
V
3.8
V
12
V
12
V
3.3
V
3.8
V
REG
HD
MI_
3.3
V
PC
ON
T_2
IC3
08
IC3
07
DA
C3.
3V
5.8
V
3.3
V
IC3
05
REG
IC3
03
HD
MI_
1.2
V
IC7
04
IC3
09
PC
ON
T_C
OR
E
0.9
V
VR
EF
_0.
9V
IC3
10
IC3
11
(B
ack
En
d)
PC
ON
T_3
PC
ON
T_3
PC
ON
T_3
PC
ON
T_3
PC
ON
T_3
DC
DC4
V
IC1
01
PC
ON
T_3
3.
3VA
1.
2VA
5V
HD
MI5
V
REG
5.8
V
HD
MI
Ho
t P
lu
g
US
B5V
US
B5V
REG
5V
5.8
V
5V
US
B
REG
Ｉ
Ｆ
-C
ON
IC
15
03
3.3
V
3.3VA
Fl
as
h
GP
IO
JT
AG
5.8
V
12
V
IC7
05
REG
IC3
14
IC6
01
IC6
02
PC
ON
T_3
US
B_
VB
US
_P
CO
NT
1
US
B_
VB
US
_P
CO
NT
2
Et
he
r P
HY
CORE_STB3.3V (= 3.3VA)
Et
her
_3.
3V
WL
AN
REG
REG
VI
DEO
_Bu
ffe
r3.
3V
3.3
V
3.8
V
-5V
-6V
Au
di
o
DAC
/AM
P
IC
90
1
Vi
de
o B
uf
fe
r
IC
10
03
VI
DEO
_Bu
ffe
r-5
V
DAC3.3V
IC1
00
1
IC1
00
2
PC
ON
T_3
PC
ON
T_2
Au
dio
DAC
_3.
3V
OPT
ICA
L
IC
90
4
3.3VA
UNSW12V
UNSW3.3V
to
FL
20
0
PS1501
FC
C2
0 5
01
AJ
PS301
DC JACK
UN
SW
12
V
1ch
DCDC
FH
C2
0 3
22
AJ
IC3
12
PC
ON
T_2
J30
1
DC
DC
-6V
1ch
DCDC
PS302
FC
C2
0 1
02
AJ
IC3
13
UNSW 3.3V
3-5E