Sony RM-PJM15, Руководство по обслуживанию

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3-5
VPL-PX32
3-4. C Board
3-4-1. Timing Generator
The following timing pulses are generated from the HSO, VSO, and CLOCK by the CXD9512Q of the
BC board and supplied to the C board.
In the C board, all signals are level shifted to 5 V and sent via the buffer as well.
HCK1, HCK2: Clock for the H shift register drive of the panel
HST:
Start pulse for the H shift register drive of the panel
VCK: Clock for the V shift register drive of the panel
VST: Start pulse for the V shift register drive of the panel
ENB: Enable signal of the gate selection pulse
FRP: Reverses the top and bottom of video signals centering around the reversal pulse and
SIG CENT voltage
PRG: Pulse which regulates the width of the first SID level
PCG: Pulse which improves uniformity
RGT: Reverses the left and right of the screen, controls the drive direction of the H shift
register
DWN: Reverses the left and right of the screen, controls the drive direction of the V shift
register
3-4-2. LCD Driver Control Pulse
INV CONT: Reverses the polarity of the CLK for MCLK
DLY CONT: Adjusts the phase of the CLK for the MCLK in the 180
d
range
These pulses optimize the sampling phase of the video signal.
POSCONT1, 2: Adjusts the position of the 1 and 2 outputs for the video input signal.
Sets the optimum timing for inputting signals to the LCD panel through 16 different combinations of
the output.