Sony PMC-222V, Руководство по обслуживанию

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Pin No.
1
2
3 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22 to 29
30
31
32
33 to 42
43
44 to 48
49
50
51
52 to 59
60
61
62 to 64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83 to 90
91 to 95
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
O
O
O
I/O
O
O
O
O
I
O
O
I
I
O
I
O
I
I
I
I
O
I
O
Description
P1.0 of 8051
Digital VCC
P1.1 to P1.7 of 8051
Digital ground
X’tal input
X’tal output
RxD of 8051
TxD of 8051
INT0 of 8051
INT1 of 8051
T0 of 8051
T1 of 8051
WR of 8051
RD of 8051
PSEN of 8051
Data bus bit 0 to 7 of 8051
Digital VCC
Digital ground
Test pin, Normally pull low
Address bus bit 0 to 9 of 8051
Address bus bit 10 of 8051, SRAM chip enable
Address bus bit 11 to 15 of 8051
Address latch enable
Test data latch signal
Digital ground
CL480 host data interface
CL480 host data strobe signal
CL480 host data read/write signal
CL480 host address interface
Extention I/O Port enable signal
PLL clock output mode 1: 16.9344MHz 0: 11.2896MHz
Reset signal output. Its output is controlled by/PWRCTLI signal.
Analog ground
PLL charge pump output
PLL VCO input
Analog VDD
PLL test pin, It should be connected to SYSRST pin for normal operation.
PLL clock output, Its output is controlled by/PWRCTLI signal.
PLL clock input
Power-on reset signal output. It’s output is controlled by/PWRCTLI
Power-On reset signal input
Audio switch signal
NTSC/PAL indicator input, internal pull-down
Board test mode selection input, internal pull-up
Digital VCC
Digital ground
Mute signal output
Key scan matrix column 7 to 0
Key scan matrix row 7 to 3
Pin Name
P1.0
VCC
P1.1 to P1.7
GND
X1
X2
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PSEN
BD0 to BD7
VCC
GND
CPUTST
A0 to A9
A10/SRAM
A11 to A15
ALE
KEYWR
GND
HD7 to HD0
DS
R/W
HSEL2 to HSEL0
ENH
CLK-HIGH
RESET
AGND
CPO
VCI
AVDD
PLL/PD
DA-XCLK
CD-BCK
SYSRST
480RST
AUD-SW
NTSC
TEST
VCC
GND
MUTE
COL7 to COL0
ROW7 to ROW3
VCD BOARD U1008 VIS2088 (VCD SYSTEM CONTROL)