Sony PCV-J150 - Vaio Desktop Computer, Руководство по обслуживанию, Страница: 12 / 27

3-1 PCV-J150 (UC)
Confidential
SECTION 3
MOTHER BOARD DESCRIPTION
3-1. A7S-AV MOTHER BOARD
3-
2
F
o
rm fa
cto
r
•
Me
et
In
te
l Mi
cr
oA
T
X
L
at
es
t ver
si
o
n
s
p
e
cific
ati
on
-Max
im
u
m
9
.6
in
ch
es
x
9
.6
in
ch
es
(2
4
4
m
m
x
2
4
4
m
m
)
-Hei
g
h
t res
trictio
n
s
of
Micr
oA
TX
v
ers
io
n
1.
0
3-
3
E
xpa
nsio
n S
lot
s
•
3
2
b
it
M
a
st
er
PC
I
B
u
s sl
o
ts
-S
up
po
rts
3.
3
V
/5
.0
V
PC
I
B
u
s
In
te
rf
ac
e
3-
4
C
on
ne
cto
rs
an
d Head
er
s
•
S
in
g
el
S
o
c
k
et
A
f
o
r CP
U
N
o
te
s:
Heat
si
n
k
s
p
a
ce f
o
r G
ig
a
A
th
lo
n
•
T
w
o 1
6
8
p
in
D
IM
M
s
o
c
k
et
(
g
o
ld
p
lat
ed)
N
o
tes:L
ayo
u
t p
o
si
ti
o
n
(
Screw hol
e)
•
A
T
X
po
we
r s
u
pp
ly
po
we
r c
o
n
n
ec
to
r
, P
o
we
r S
u
pp
ly
F
an
co
n
n
ec
to
r
•
O
n
e
F
D
D
/ T
w
o I
D
E
Co
nn
ec
tor
s
•
4
-p
in
CD
-R
O
M
a
u
di
o
in
pu
t
(s
te
re
o
) c
o
nn
ec
tor
•
4
-p
in
A
U
X
au
di
o
in
pu
t
(s
te
re
o
)
co
nn
ec
tor
•
4-
pi
n V
ide
o
au
d
io
i
n
p
u
t
(s
te
re
o)
c
o
n
n
ec
tor
•
T
w
o P
S
2
c
o
nn
ec
tor
(
K
ey
bo
ar
d
, Mo
us
e
)
•
T
re
e U
S
B
p
o
rt
c
o
n
n
ec
to
r (
3
f
o
r rear
I/O)
•
O
n
e P
ar
all
el
(2
5
p
in
) co
n
n
ect
o
r
•
O
n
e IEEE13
9
4
(
6
p
in
)
st
a
n
d
ar
d
i
n
te
rf
ace co
n
n
ect
o
r
•
O
n
e V
G
A
co
n
n
ect
o
r
•
On
e Seri
al
(C
OM
1,
9p
in
) c
o
n
n
ec
to
r i
n
re
ar
I/
O (w
/A
ud
io
c
o
n
n
ec
to
r)
•
L
in
e I
n
/M
ic
I
n
/H
ea
dp
ho
ne
O
u
t m
in
i-
ja
c
k (
w
/S
er
ia
l c
o
nn
ec
tor
)
•
Po
we
r &
S
le
e
p
SW
/HDD
Ac
c
L
E
D
/R
eset
S
W
/S
p
eak
er
h
ead
e
r (
F
ro
n
t P
an
el
I/
O
h
ead
e
r)
•
T
h
re
e
C
o
o
li
n
g
F
an
c
o
n
n
ec
to
r (C
PU
, PS
Chasis)
•
C
le
ar
pa
ss
w
or
d he
ad
e
r
(f
or
B
IOS
)
3-
5
G
ra
ph
ics
•
Si
li
co
n
I
n
te
g
rat
ed
Sy
st
ems
Si
S7
3
0
s
w
/Si
S3
0
0
G
rap
h
ics en
g
in
e.
3-
1
O
ve
rvie
w
This
documen
t
des
c
ribes
t
he
s
pecific
a
tion
f
o
r
the
A7
S
-A
V
mother
boar
d f
o
r P
C
V
-J
150
.
•
Bo
ar
d S
p
e
cific
ati
on
: I
n
te
l Mi
cr
oA
T
X
L
at
es
t ver
si
o
n
co
m
p
at
ib
le
•
P
ro
cesso
r:
S
u
p
p
o
rt
s S
in
g
le
S
o
c
k
et
A
-b
ase
d
A
M
D
”
At
hl
o
n
/
Du
ro
n
” P
ro
cesso
rs
, al
l sp
e
ed
s,
v
o
lt
a
g
es,
b
u
s
fr
e
q
u
en
ci
es.
•
North & South Bridge System Chipset: Features the Silicon Integrated Systems SiS730s system controller with su
pp
ort
fo
r a
20
0M
Hz
F
ron
t S
ide
B
u
s;
up
t
o
512MB
of
P
C
133/P
C
100
S
D
RAM.
•
S
u
p
er
-S
o
u
th
Br
id
g
e
S
y
st
em
P
C
Is
et:
S
il
ico
n
I
n
te
g
rat
ed
S
y
st
ems
S
iS
7
3
0
s with
a P
C
I S
u
p
er
I
/O
I
n
te
g
rat
ed
Peri
ph
er
al
C
o
n
tr
o
ll
er
wi
th
s
u
pp
ort
fo
r Ul
tr
a
DM
A/
66
or
10
0;
A
C
’9
7
a
u
di
o;
•
F
ro
n
t
S
id
e
Bu
s
(F
S
B
) : Ca
n
su
p
p
o
rts
2
0
0
/133/100MHz
FSB.
•
E
x
te
rn
a
l US
B :
3p
or
t,
US
B
V
er1
.1
,
US
B C
o
n
n
ec
to
r R
e
ar
P
ane
l
x 3 c
h
•
M
a
in
M
e
m
o
ry
:
T
w
o
16
8-
pi
n DI
MM
s
o
c
k
et
s (S
u
p
p
o
rt
S
D
RA
M 64
/2
5
6
M
B
,
M
a
x
im
u
m
51
2M
B
y
te
No
nE
C
C
)
•
ID
E
P
o
rt
s:
T
w
o p
o
rt
s
A
T
A
Ultra
D
M
A
3
3
/6
6/1
0
0
M
H
z en
abl
e
•
Ha
rd
wa
re
m
o
ni
to
ri
ng
F
A
N
(C
PU
,P
S,
C
h
a
ss
is
) s
p
e
ed
m
o
ni
to
r
/ C
P
U
T
em
p
/s
en
so
r
•
P
C
I E
x
p
ans
io
n
s
lot
s:
P
ro
v
id
e
s t
h
re
e 32
bi
t
P
C
I R
ev2
.2
e
x
p
ans
io
n
s
lot
s,
wh
ic
h
c
an
s
u
pp
ort
B
u
s
M
a
st
er
P
C
I c
ar
ds
.
•
On
bo
ar
d
(M
ot
he
r B
o
ar
d
) A
C
’97
V
er2.
1
Au
di
o C
o
d
e
c (A
DI
AD
18
81
A)
•
O
n
b
o
ar
d
i
L
IN
K
(
IEEE1
3
9
4
) f
u
n
ct
io
n
(
O
H
C
I Co
n
tr
o
ll
er
,
D
R
V
/RC
V
& Co
n
n
ect
o
r)
•
S
u
sp
en
d t
o
R
A
M
s
u
pp
ort
(W
ak
e up
fr
om
K
eyb
oa
rd
,
L
A
N
,
USB
an
d
P
o
wer
b
u
tton)
•
Pr
og
ra
mmabl
e B
IOS
(F
la
sh
E
E
P
R
O
M
)
•
BI
O
S
S
u
sp
en
d
M
o
d
e
LED
S
u
p
p
o
rt
(
P
o
w
er
O
N
: G
ree
n /
S
u
sp
en
d
:
O
ran
g
e
)
•
W
ak
e O
n
Ri
ng
PCI Card
S
u
pports W
ake ON
R
in
g
acti
v
ity
•
N
o
Q
-s
al
t cap
aci
to
rs
•
H
eat
si
n
k
g
ro
u
n
d
in
g
s
u
p
p
o
rt
f
o
r CP
U
•
PC
9
9
C
o
mp
li
an
t
•
Mo
de
m
: P
C
I Ca
rd
S
u
p
p
o
rt
(
V
.9
2:
D
river
s
o
ft
w
ar
e
su
p
p
o
rt
)
•
O
p
er
at
ing
S
y
st
em
S
u
p
p
o
rt
s: W
in
dows
Mille
n
nium E
d
ition
3-
1-1
Ma
jor
Mo
un
t Op
tio
n C
o
m
p
o
n
e
n
ts
•
A
C
9
7
sh
a
ri
n
g
r
esi
st
o
rs