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DIGITAL BOARD IC503 CXD2605Q (Master DAT-DSP)
Pin No.
Pin Name
I/O
Function
1
A8
O
External RAM address output
2
A9
O
External RAM address output
3
VDD
—
+5V
4
A10
O
External RAM address output
5
A11
O
External RAM address output
6
A12
O
External RAM address output
7
A13
O
External RAM address output
8
A14
O
External RAM address output
9
XWE
O
External RAM write enable signal output
10
XOE
O
External RAM output enable signal output
11
XEAN
O
External addressing enable signal output. (Not used in this set.)
12
TST1
I
Test input (Fixed at “L” level.)
13
XT1O
O
X’tal oscillation circuit 1 output
14
XT1I
I
X’tal oscillation circuit 1 input
15
VSS
—
Ground
16
XRST
I
Reset input. “L” for reset.
17
CLKO
O
System clock output. (The frequency is 4.9152 MHz when SELC is set “L” and 8.192 MHz
when SELC is set “H”.) (Not used in this set.)
18
MINT
O
Control byte (1). Bit 1: Q code decode (intercurve detection) output when “L” and BCK clock
output by RX-PLL when “H”. (Not used in this set.)
19
ATSY
I
ATF sync signal input
20
MCLK
O
Channel clock (fch) output (Not used in this set.)
21
DREF
O
SBSY cycled Duty 50 signal output
22
SBPM
O
Control byte (1). Bit 1: Output of monitor signal for data transfer to and from microcomputer
when “L” (“L” to permit transfer) and F256 clock output by RX-PLL when “H”.
(Not used in this set.)
23
EXCK
I
Input of clock for data transfer to and from main microcomputer (IC501).
24
SDSI
I
Serial data input from main microcomputer (IC501).
25
SDSO
O
Serial data output to main microcomputer (IC501).
26
SBSY
O
Output of frame sync signal for data transfer to and from main microcomputer (IC501).
27
PLRF
O
Output of PLL clock divided by 5880. (Not used in this set.)
28
CCLK
O
9.8304MHz output when SELC is “L” and 12.288MHz output when SELC is “H”.
(Not used in this set.)
I
Mute input. Set “H” to mute, but REC monitor sound will not be muted.
O
Mute monitor. “H” in muting.
O
RX-PLL lock monitor signal output. “L” in locking.
I
Area signal input. (“L” to enable AREA signal and “H” to disable AREA signal.)
O
RF associated C1 check result monitor signal output. (Not used in this set.)
I
Test pin (Fixed at “H” level.)
O
Control byte (1). Bit 1: RF-PLL clock output when “L” and F128 clock output by RX-PLL
when “H” (Not used in this set.)
I
Test pin (Fixed at “L” level.)
I
Playback RF signal input
38
XCS
I
Input of chip select signal for data transfer to and from microcomputer. “L” to permit transfer.
39
SWP
I
RF switching pulse. “L” to select A track and “H” to select B track.
40
VSS
—
Ground
41
PIPC
O
Output of ATF pilot signal/descrimination signal for recording signal. “H” to output pilot
signal.
42
REPB
O
REC/PB descrimination signal output. “H” for REC mode.
43
REDT
O
Recording signal output.
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