Sony IPELA SNC-Z20N, Руководство по обслуживанию

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4-4
SNC-Z20N/Z20P (E)
O N
1 2 3 4
Normal setting
(0, 0, 0, 0)
O N
1 2 3 4
Test mode
(1, 1, 1, 0)
4-3-6. System Memory
The system memory (SDRAM, IC607 and IC609) that has
a capacity of 32 MB stores the Main CPU (IC606)
operation program or Web contents from flash memory
when the power is turned on.
Other areas are used to secure an area of approximately 8
MB as internal memory.
The system memory also temporarily stores the JPEG
compression data transferred from IC703 at high speed
using a DMA controller built in Main CPU (IC606) or the
saved image of an alarm buffer.
4-3-7. RTC Circuit
A dated watch function is realized using RTC (Real Time
Clock, IC602). The RTC is backed up by a rechargeable
battery (BT601). The watch data of RTC can be read and
written by Main CPU (IC606).
4-3-8. Reset Circuit
A power-on reset signal is output to the Main CPU
(IC606), system ROM (flash memory, IC610 and IC611),
or PHY chip (IC801) using a reset circuit (IC603). The
reset circuit also has a function for outputting a reset signal
using manual reset switch S603 or for outputting a reset
signal by the detection of a voltage decrease.
4-3-9. DIP Switch Block
DIP switch S602 is used to switch the operation mode of a
system. When the power is on, Main CPU (IC606) reads
the state of the DIP switch so as to judge the operation
mode. Usually, SW1 to SW4 are all set to “0”.
In the test mode, SW1 to SW3 are all set to “1”, and SW4
is set to “0”.
4-3-10. Clock Buffer Block
Clock buffer IC605 buffers a clock of 30 MHz from Main
CPU (IC606) and supplies a stable clock to the system
memory (SDRAM, IC607 and IC609) (SR1_CLK and
SR2_CLK), PC card controller (IC203) (PC_CLK), or
MJPEG controller (IC703) (SYCLK).
4-3-11. PC Card Control Block
A PC card is accessed through CN201 and a PC card slot
using Main CPU (IC606) and a PC card controller (IC203).
The PC card of 3.3 V or 5 V power supply can be used by
PC card power selection circuit IC204.
4-3-12. Network Control Block
Network communication is controlled through Main CPU
(IC606), the PHY chip of IC801, and RJ45 of CN802. The
communication between the Main CPU (IC606) and PHY
chip (IC801) is performed by MII based on the IEEE
802.3u standard. The transfer rate (10Base-T/100Base-
TX) or communication mode (full duplex/half duplex) can
also be switched.
4-3-13. Reset Switch
The reset switch (S601) is used to return the system to the
factory setting.
To return to the factory setting, turn on the power while
pressing and holding S601.
4-3-14. Sensor Input Circuit Block
The sensor input circuit inputs the external sensor signal
from the terminal board connector of CN2 using a
photocoupler (PH801) (three ports). The output signals
(EXINT[02:00]) from the photocoupler are input to the
interrupt controller of MJPEG control (IC703) and
recognized as an interrupt signal (XSHINT[2:0]) of Main
CPU (IC606).