Sony ICF-M33RDS, Руководство по обслуживанию

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4-6. IC PIN FUNCTION DESCRIPTION
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KEY BOARD IC101
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PD753012AGC-F05-3B9 (SYSTEM CONTROLLER, LCD DRIVER, KEY CONTROL)
Pin No. Pin Name I/O Description
1 to 20 LCD12 to LCD31 O Segment drive signal output to the liquid crystal display (LCD101)
21 to 24 COM0 to COM3 O Common drive signal output to the liquid crystal display (LCD101)
25 BIAS O Liquid crystal display drive bias control output terminal Not used (open)
26 VLCD0 I Develop liquid crystal display drive voltage input terminal
27, 28 VLCD1, VLCD2 I Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
29 to 32 KS0 to KS3 O Key scan signal output of the key matrix (S102 to S117)
33 VSS — Ground terminal
34, 35 LIGHT O Liquid crystal display back light LED drive signal output terminal “L”: back light on
36 POWER O PLL low-pass filter power supply on/off control signal output terminal “L”: power on
37 FM O RDS decode circuit power supply on/off control signal output terminal “L”: power on
38 VDET1 I Battery voltage detect signal input terminal “L” is input at low voltage
39 CLK/RX O
Clock signal output for the receive level control Not used (open)
40 DTA/RX O
Data output for the receive level control Not used (open)
41 AF AUTO I
AF mode selection signal input terminal “L”: manual mode, “H”: auto mode
Fixed at “L” in this set
42 TEST I
Test mode input terminal “L”: test mode Not used (open)
43 CLK/RDS I
Serial data transfer clock signal input from the RDS decoder (IC3)
44 DTA/RDS I
Serial data input from the RDS decoder (IC3)
45 SD I
Station detector detect input from the CXA1019M (IC1)
Stop level for SEEK, BTM, etc. is determined SD is present at input of “L”
46 BUZZER O
Beep sound drive signal output to the CXA1019M (IC1)
47 DTA/PLL O
Serial data output to the FM/AM PLL (IC2)
48 LAT/PLL O
Serial data latch pulse signal output to the FM/AM PLL (IC2)
49 CLK/PLL O
Serial data transfer clock signal output to the FM/AM PLL (IC2)
50 LAT/RX O
Latch signal output for the receive level control Not used (open)
51 HALT O
“H” is output at halt mode Not used (open)
52 KEYTEST O
“L” is output at test mode
53 MUTE O
Muting on/off control signal output terminal “L”: muting on
54 VDD —
Power supply terminal (+3V)
55 XT1 I
Main system clock input terminal (4.332 MHz)
56 XT2 O
Main system clock output terminal (4.332 MHz)
57 IC —
Connected to power supply (+3V)
58 X1 I
Sub system clock input terminal (32.768 kHz)
59 X2 O
Sub system clock output terminal (32.768 kHz)
60 SFT CLK O
Alert signal output for the shift clock circuit “L”: on, “H”: off Not used (open)
61 PS MODE I
Station name switch (S101) input terminal “L”: station, “H”: clock
62 to 67 KR0 to KR5 I
Key return signal input of the key matrix (S102 to S117)
68 RESET I
System reset signal input from the reset signal generator (IC103) “L”: reset
“L” is input for several 100 msec after power on, then it changes to “H”
69 to 80 LCD0 to LCD11 O
Segment drive signal output to the liquid crystal display (LCD101)
Ver 1.1 2000. 01