Sony HSR-X200, Руководство по обслуживанию

Страница: 44 / 78

6-2 (E)
HSR-X200/X200P
(2) DM-B
a. ASIC Operations IC251
Audio A/D, D/A.
Single channel audio signal digital conversion/
analog conversion.
8 bit sample frequency 8 kHz
MJPEG Coder
Functionality for compression/expansion of
motion JPEG images and for simultaneous
compression/expansion.
Video Encoder
Forms chroma signal according to digital
chrominance signals. (NTSC/PAL)
Video D/A
Converts digital brilliance signal and outputs it
as analog.
Converts digital chroma signal and outputs it as
analog.
Digital I/F
Interface circuit for digital data of MPX and
HDR.
IDE I/F
Interface circuit for IDE hard disk.
BUS Arbitration SDRAM CTL
Control circuit for arbitration of bus and exter-
nal SDRAM.
I/F
Interface circuit for Flash Memory, PC Card,
and CF Card.
UART
Port for servicing.
When overwriting of firmware by CF fails,
firmware is overwritten by connecting this port
to the RS-232-C port of a PC with an adapter.
SIO
Interface serial data for sub-processor.
CPU
Controls all ASIC circuits.
Thumbnails
Pixel conversion circuit for formation of
thumbnails.
b. SDRAM IC252, 253
128 Mbit x 2 short-term image storing region for
non-compressed images and compressed images.
c. PLL
Forms 4 Fsc (14.4MHz) into 108 MHz by multi-
plying it 7.5 times.
d. Flash ROM IC227
Stores the program for ASIC drive in the Flash
ROM.
When the power is turned on, the program is
loaded to ASIC from this Flash ROM.
e. CF Interface Circuit IC221, 222, 223, 224, 225,
226, 229, 231
Buffer circuit for I/O to CF card.
I/O through buffer using LCX245.
f. PC Card Interface Circuit IC232, 233, 234, 235,
236, 237, 238, 239
Buffer circuit for I/O to PC Card.
Converts 3.3 V to 5 V level using translating
tranceiver LVX3245 and performs buffering.
This Flash ROM and CF interface is on the same
bus with the PC Card interface.
g. HDD Interface Circuit IC241, 242, 243, 244, 245
I/O buffer circuit for 3.5 inch IDE hard disk.
Converts 3.3 V to 5 V level using translating
tranceiver LVX3245 and performs buffering.
h. RESET IC247
ASIC external reset circuit.
i. Synch Insertion Circuit Q2501, 2502, 2503
Circuit for inserting the synch signal into the D/A
converted brilliance signal.
(3) DM-C
a. Sub-processor IC271
Control of KEY input, external device input, LED,
ASIC, DECODER, EEPROM, RS-232-C, and RS-
485.
b. EEPROM IC281
Save data circuit. Non-volatile memory.
c. RESET IC272
External reset circuit.
d. Power outage detection circuit. IC273
e. RS-232-C communications circuit. IC274, 275, 276
Interface for sending/receiving external RS-232-C
signals.
f. RS-485 communications circuit. IC278, 279, 280,
281
Interface for sending/receiving external RS-485
signals.
(4) PC-1 CF Adapter Circuit
(5) OP-1 Front Right IC601
Circuit for front KEY input, JOG and SHUTTLE.
LED activation circuit. (LED lights when serial data is
being converted to parallel.)