57
HCD-XGV6/XGV8/XGV10AV
Description
Pin Name
Pin No.
I/O
74
NVOEL
O
Out enable signal output to memory
75
LVS4
—
Ground
76
DRBS
O
Bank select address output to memory
77
DRDQM0
O
Lower byte mask of memory
78
DRDQM1
O
Upper byte mask of memory
79
IVS5
—
Ground
80
NC
—
Not used (open)
81
SYSRST
I
System reset signal input
82
IRDIN
I
Not used (Connected to ground)
83
NC
—
Not used (open)
84
VDD1
—
Power supply (+2.5V)
85
V16M
I/O
Not used (open)
86
DOUT
O
Digital audio data output (Not used)
87
L_CDLRCK
I
D/A interface, L/R clock input
88
LRCK
O
D/A interface, L/R clock output
89
VSS1
—
Ground
90
L_CDDATA
I
Serial data input from D/A interface
91
PCMD
O
Serial data output to D/A interface
92
L_CDBCK
I
Bit clock input (2’s COMP) from D/A interface
93
BCK
O
Bit clock output (2’s COMP) to D/A interface
94
EMPH
O
Not used (open)
95
L_SQSO
I
SubQ 80bit and PCM peak level data input
96
SQSO
O
SubQ 80bit and PCM peak level data output
97
VDD2
—
Power supply (+2.5V)
98
L_SQCK
O
SQSO read out clock output
99
SQCK
I
SQSO read out clock input
100
SBSO
O
Not used (open)
101
EXCK
I
Not used (Connected to ground)
102
DATA
I
Serial data input from CPU
103
L_DATA
O
Serial data output to CPU
104
VSS2
—
Ground
I
System reset signal input (L:reset)
O
System reset signal output (L:reset)
I
Not used (Connected to ground)
O
Latch signal output to CPU
I
Latch signal input from CPU
O
Serial data clock output
I
Serial data clock input
I
SENS signal input
O
SENS signal output
O
SENS serial data read clock output
115
SCLK
I
SENS serial data read clock input
116
VDD3
—
Power supply (+2.5V)
117
ATSK
I/O
Not used (Connected to ground)
118
XUGF
O
Not used (open)
119
XPCK
O
Not used (open)
120
L_GFS
I
GPS signal input
121
GFS
O
GPS signal output
122
VSS3
—
Ground
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