56
HCD-VX555/VX555J
• IC502 M30622MGA-A45FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42, 43
44
45
46
47
48
49
50
51
I/O
I
O
O
O
O
—
—
I
—
O
O
I
O
—
I
—
I
I
—
I
I
O
—
O
—
O
—
O
I/O
I/O
O
I
O
O
O
I
I
—
I
—
I
—
I
I
O
—
—
—
—
—
Description
Internal status (SENSE) signal input from the CXD3068Q (IC101)
Sense serial data reading clock signal output to the CXD3068Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3068Q (IC101)
Not used (open)
Not used (open)
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
Ground terminal
Muting on/off control signal output to the CXD3068Q (IC101) “H”: muting on
Clock selection signal output to the CXD3068Q (IC101) “L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
Reset signal input from the system controller (IC501) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
Main system clock output terminal (10 MHz)
Ground terminal
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
Non-maskable interrupt input terminal (fixed at “H” in this set)
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
Not used (open)
Interrupt request signal input from the CL680 (IC505)
Horizontal sync signal input
Burst gate pulse signal output
Not used (open)
PWM3 signal output to the CXA2581N (IC103)
Not used (open)
PWM2 signal output to the CXA2581N (IC103)
Not used (open)
PWM1 signal output to the CXA2581N (IC103)
I
2
C clock signal
I
2
C data signal
Serial data output to the FLASH writer
Serial data input from the FLASH writer
Serial data transfer clock signal output to the FLASH writer
RTS signal to the FLASH writer
Serial data0 output to the CL680 (IC505)
Serial data0 input from the CL680 (IC505)
Data reading clock signal input from the CL680 (IC505)
Not used (open)
Ready signal input terminal Not used (fixed at “H”)
Not used (open)
Hold signal input terminal from the FLASH writer
Not used (open)
OSD language select input terminal “H”: English, “L”: China
Vertical sync signal input
Bus write signal output to the FLASH writer
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (fixed at “H”)
Pin Name
SENSE
SENSE CLK
RESOLUTION
CHROMA LEVEL
DSP CLK
TSENS
REMOTE IN
BYTE
CN VSS
DSP MUTE
CTRL1
XRESET
XOUT
VSS
XIN
VCC
NMI
SCOR
DSENS
CL680INTERRUPT
H.SYNC IN
BGP
PWM3(BD)
PWM2(BD)
PWM1(BD)
12C.CLK
12C.DATA
DATA1O
DATA1I
CLK1
RTS1
DATAO
DATAI
CLK1
P.ON
BUS XRDY
BUS
BUS XHOLD
BUS
OSD.LANGUAGE
VSYNC
BUS XWRL
LO.BOOST
AUDIO MUTE
LOAD OUT
LOAD IN
INSW
Содержание HCD-VX555
Страница 14: ...14 HCD VX555 VX555J VIDEO BOARD SIDE A J301 CN501 CN301 1 2 3 CN503 SL503 SL502 SL501 CHECK LED CN502 ...
Страница 29: ...29 29 HCD VX555 VX555J 6 5 SCHEMATIC DIAGRAM MAIN SECTION 2 4 See page 58 for IC Block Diagrams IC B D ...
Страница 35: ...35 35 HCD VX555 VX555J 6 11 SCHEMATIC DIAGRAM AMP SECTION ...
Страница 39: ...39 39 HCD VX555 VX555J 6 15 SCHEMATIC DIAGRAM PANEL SW SECTION ...
Страница 41: ...41 41 HCD VX555 VX555J 6 17 SCHEMATIC DIAGRAM LEAF SW SECTION ...
Страница 43: ...43 43 HCD VX555 VX555J 6 19 SCHEMATIC DIAGRAM DRIVER SECTION See page 59 for IC Block Diagrams IC B D ...
Страница 46: ...46 46 HCD VX555 VX555J 6 22 SCHEMATIC DIAGRAM VIDEO SECTION 2 3 See page 23 for Wavefoms ...
Страница 47: ...47 47 HCD VX555 VX555J 6 23 SCHEMATIC DIAGRAM VIDEO SECTION 3 3 See page 23 for Wavefoms ...
Страница 49: ...49 49 HCD VX555 VX555J 6 25 SCHEMATIC DIAGRAM TRANS SECTION ...