Sony HCD-V707, Руководство по обслуживанию

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• VIDEO BOARD IC901
µ
PD780016YGF-012-3BA (IIC INTERFACE CONTROLLER)
Pin No. Pin Name I/O Function
1 to 8 P80 to P87 I
Not used (fixed at “L”)
9 TEST I Test terminal (fixed at “L”)
10 X2 O
Main system clock output terminal (5 MHz)
11 X1 I
Main system clock input terminal (5 MHz)
12 VDD — Power supply terminal (+5V)
13 XT2 O
Sub system clock output terminal Not used (open)
14 XT1 I
Sub system clock input terminal Not used (fixed at “H”)
15 RESET I Reset signal input from the master controller (IC301) “L”: reset
16 P00 I
Inputs the boundary point control (phase fix) for CXD1854Q (IC301) (fixed at “L”)
17 P01 I
Inputs the boundary point control (phase switch) for CXD1854Q (IC301) (fixed at “L”)
18 QINT I
Interrupt status input from the CD mechanism controller (IC701)
19 to 22 P03 to P06 I
Inputs the boundary point control (phase 0 to 3) for CXD1854Q (IC301) (fixed at “L”)
23 VDD —
Power supply terminal (+5V)
24 AVDD —
Power supply terminal (+5V) (for A/D conversion)
25 to 32 P10 to P17 I
Not used (fixed at “L”)
33 AVSS —
Ground terminal (for A/D conversion)
34 CMD0 I/O
35 CMD1 I/O
36 CMD2 I/O
37 CMD3 I/O
38 P24 I Not used (fixed at “L”)
39 P25 I
Not used (fixed at “L”)
40 VSS —
Ground terminal
41 P26 I Not used (fixed at “L”)
42 P27 I
Not used (fixed at “L”)
43 MREQ O
Communication request signal output to the CD mechanism controller (IC701)
44 SACK I Data acknowledge input from the CD mechanism controller (IC701)
45 CDGM I
Not used (fixed at “L”)
46 P93 I
Not used (fixed at “L”)
47 MDATA O
Serial data output to the on screen display controller (IC271) and video noise reduction (IC301)
48 MCLK O
Serial data transfer clock signal output to the on screen display controller (IC271) and video
noise reduction (IC301)
49 OS-XLAT O
Serial data latch pulse output to the on screen display controller (IC271)
50 G-XLAT O
Serial data latch pulse output terminal Not used (open)
51 G-XRST O
Reset signal output terminal Not used (open)
52 CD-XRST O
Reset signal output to the CD/video CD circuit “L”: reset
53 CDPOW O Power on/off selection signal output terminal Not used (open)
54
DOUT
O
Digital output terminal Not used (open)
55 IIC-DATA I/O
Communication data bus with the master controller (IC301) and fluorescent indicator tube
driver (IC601)
56 IIC-CLK I/O
Communication data reading clock signal input or transfer clock signal output with the master
controller (IC301) and fluorescent indicator tube driver (IC601)
57 to 64 P40 to P47 I
Not used (fixed at “L”)
65 NRON O Video noise reduction system on/off selection signal output terminal Not used (open)
66 LEVEL0 O
Level control signal output terminal Not used (open)
67 LEVEL1 O
Level control signal output terminal Not used (open)
Two-way data bus with the mechanism controller (IC701)
Pin No. Pin Name I/O Function
68 NR-XCS O
Chip select signal output to the video noise reduction (IC301)
69 P54 I Not used (fixed at “L”)
70 P55 I
Not used (fixed at “L”)
71 VSS —
Ground terminal
72 P56 I Not used (fixed at “L”)
73 P57 I
Not used (fixed at “L”)
74 to 81 P60 to P67 I
Not used (fixed at “L”)
82 to 85 P100 to P103 I
Not used (fixed at “L”)
86 to 93 P30 to P37 I
Not used (fixed at “L”)
94 to 100 P150 to P156 I
Not used (fixed at “L”)
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