70
HCD-L7HD
Pin No.
134
135
136
137
138
139
140-143
144
145
146
147
148
149
150
151
152,153
154
155
156
157,158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178-180
181
182
183
184
185-188
189,190
191,192
193
194
195
196
197
I/O
—
I/O
I
I
I
I
I
I
—
—
—
—
—
—
I
—
—
O
I
O
I/O
O
—
I/O
—
O
I/O
O
I/O
O
I/O
I/O
I
I
—
I
—
I
O
I/O
—
I/O
—
O
I/O
O
I
I
I
I
I
I
Pin Name
Vcc
AUDATA0
TRST
TMS
TDI
TCK
IRLS3-0
MD0
Vcc-PLL1
CAP1
Vss-PLL1
Vss-PLL2
CAP2
Vcc-PLL2
AUDCK
Vss
Vcc
XTAL
EXTAL
STATUS0,1
TCLK
IRQOUT
VssQ
CKIO
VccQ
TxD0
SCK0
TxD1 (MD CONT)
SCK1
TxD2
SCK2
RTS2
RxD0
RxD1 (MD CONT)
Vss
RxD2
Vcc
IRQ5
MCS7 (CS ADDA)
MCS6-4
VssQ
WAKEUP
VccQ
RESETOUT
MCS3-0
DRAK0,DRAK1
DREQ0,DREQ1
RESETP
CA
MD3
MD4
MD5
Description
Power supply terminal (1.8V)
AUD data (not used)
Reset signal input (for test)
Mode switch input (for test)
Data input (for test)
Clock signal input (for test)
External interrupt signal input
Clock mode setup terminal
Power supply terminal for PLL1 (1.8V)
External capacity terminal for PLL1
Ground terminal for PLL1
Ground terminal for PLL2
External capacity terminal for PLL2
Power supply terminal for PLL2 (1.8V)
AUD clock input
Ground terminal
Power supply terminal (1.8V)
Clock crystal terminal
Clock crystal terminal
Processer status 0,1 (not used)
Clock signal input/output (TMC or RTC) (not used)
Interrupt request output (not used)
Ground terminal
System clock input/output
Power supply terminal (3.3V)
Serial data output (not used)
Serial clock output (not used)
Serial data output
Serial clock output (not used)
Serial data output (for debug)
Serial clock output
Transmission request output
Serial data input
Serial data input
Ground terminal
Serial data input (for debug)
Power supply terminal (1.8V)
Power down signal input
Input/Output signal port C
Input/Output signal port C (not used)
Ground terminal
Interrupt request acknowledge input during standby mode (not used)
Power supply terminal (3.3V)
Reset signal output
Input/Output signal port C (not used)
DMA request acceptance input (not used)
DMA request input
Power ON reset signal input
Chip active input (not used)
Bus width setup for area 0 (fixing L)
Bus width setup for area 0 (fixing H)
Endian setup
Содержание HCD-L7HD
Страница 37: ...37 37 HCD L7HD 6 5 Schematic Diagram BD Section See page 62 for IC Block Diagrams and Wavefoms ...
Страница 39: ...39 39 HCD L7HD 6 7 Schematic Diagram MOTOR Section ...
Страница 42: ...42 42 HCD L7HD 6 10 Schematic Diagram HDD1 Section 1 2 See page 62 for Wavefoms ...
Страница 46: ...46 46 HCD L7HD 6 14 Schematic Diagram HDD2 Section 2 2 FOR MEMORY STICK NOT USED ...
Страница 49: ...49 49 HCD L7HD 6 17 Schematic Diagram MAIN Section 1 2 See page 62 for Wavefoms ...
Страница 55: ...55 55 HCD L7HD 6 23 Schematic Diagram AMP Section See page 62 for Wavefoms ...
Страница 57: ...57 57 HCD L7HD 6 25 Schematic Diagram DISPLAY Section See page 62 for Wavefoms ...
Страница 59: ...59 59 HCD L7HD 6 27 Schematic Diagram CONTROL Section See page 62 for IC Block Diagrams ...
Страница 61: ...61 61 HCD L7HD 6 29 Schematic Diagram POWER Section ...
Страница 95: ...95 HCD L7HD MEMO ...
