Sony HCD-GX90D, Руководство по обслуживанию

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60
HCD-GX90D/RV800D
Pin No.
128, 129
130
131
132
133, 134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172 to 176
I/O
—
O
I
O
—
O
I
I
I
—
O
—
O
—
O
I
I
O
I
—
I
I
—
I
—
I
—
O
I
O
I
—
O
I
I
I
I
I
—
O
I
—
I/O
Pin Name
VCCA3, VCCA2
PDO
PDHVCC
FDO
GNDA2, GNDA1
SPO
VC2
MDIN2
MDIN1
VCCA1
CLVS
VSS
MDSOUT
VDD
MDPOUT
DEFECT
GSCOR
EXCK
SBIN
VSS
SCOR
WFCK
VDD5V
XRCI
VDDS
C2PO
VDD
DBCK
BCLK
DDAT
MDAT
VSS
DLRC
LRCK
XRST
IFS0
IFS1
XTAL
VSS
XTA2
XTA1
VDD
D0 to D4
Description
Power supply terminal (+3.3V) (analog system)
Signal output from the charge pump for phase comparator
Middle point voltage input terminal for RF PLL
Signal output from the charge pump for frequency comparator
Ground terminal (analog system)
Spindle motor control signal output
Middle point voltage (+1.65V) input terminal
Spindle motor servo drive signal input
MDP input terminal
Power supply terminal (+3.3V) (analog system)
Control signal output for selection the spindle control filter constant at CLVS
Ground terminal (digital system)
Frequency error output terminal of internal CLV circuit
Power supply terminal (+3.3V) (digital system)
Phase error output terminal of internal CLV circuit
Defect signal input terminal Not used
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
Subcode serial data reading clock signal output to the digital signal processor
Subcode serial data input from the digital signal processor
Ground terminal (digital system)
Subcode sync (S0+S1) detection signal input from the digital signal processor
Write frame clock signal input from the digital signal processor
Power supply terminal (+5V)
RAM overflow signal input terminal Not used
Power supply terminal (+5V) (digital system)
C2 pointer signal input from the digital signal processor
Power supply terminal (+3.3V) (digital system)
Bit clock signal (2.8224 MHz) output terminal Not used
Bit clock signal (2.8224 MHz) input from the digital signal processor
PCM data output terminal Not used
Serial data input from the digital signal processor
Ground terminal (digital system)
L/R sampling clock signal (44.1 kHz) output terminal Not used
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
Reset signal input from the mechanism controller “L”: reset
Interface selection signal input terminal Fixed at “L” in this set
Interface selection signal input terminal Fixed at “H” in this set
33.8688 MHz clock signal input terminal
Ground terminal (digital system)
System clock output terminal (33.8688 MHz)
System clock input terminal (33.8688 MHz)
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the mechanism controller